【2】序列检测

序列检测

（1）不重复序列检测

检测序列1001，输入序列为1001001。只能检测到一次1001序列

状态机法

• 状态转移图如下：

module sequence_detect_fsm(
	input clk,
	input rst_n,
	input data,
	output reg valid_o
);
parameter 		IDLE = 5'b0000_1,
			    S0   = 5'b0001_0,
			    S1   = 5'b0010_0,
			    S2   = 5'b0100_0,
			    S3   = 5'b1000_0;

reg[4:0]  cs, ns;

always@(posedge clk, negedge rst_n)begin
	if(!rst_n)begin
		cs <= IDLE;
	end
	else begin
		cs <= ns;
    end
end			    

always@(*)begin
	case(cs)
    	IDLE: ns = data? S0:ns;
    	S0:   ns = data? ns:S1;
    	S1:   ns = data? S0:S2;
    	S2:   ns = data? S3:IDLE;
    	S3:   ns = data? S0:IDLE;
    	default: ns = IDLE;
    endcase
end

always@(posedge clk, negedge rst_n)begin
	if(!rst_n)begin
		valid_o <= 1'b0;
    end
    else begin
		case(ns)
			S3: valid_o <= 1'b1;
			default: valid_o <= 1'b0;
		endcase
    end

end

endmodule

（2）重复序列检测

检测序列1001，输入序列为1001001。能检测到两次1001序列。

• 状态转移图如下：

①状态机法

module sequence_detect_fsm(
	input clk,
	input rst_n,
	input  data,
	output reg valid_o
);
parameter 		IDLE = 5'b0000_1,
			    S0   = 5'b0001_0,
			    S1   = 5'b0010_0,
			    S2   = 5'b0100_0,
			    S3   = 5'b1000_0;

reg[4:0]  cs, ns;

always@(posedge clk, negedge rst_n)begin
	if(!rst_n)begin
		cs <= IDLE;
	end
	else begin
		cs <= ns;
    end
end			    

always@(*)begin
	case(cs)
    	IDLE: ns = data? S0:ns;
    	S0:   ns = data? ns:S1;
    	S1:   ns = data? S0:S2;
    	S2:   ns = data? S3:IDLE;
    	S3:   ns = data? S0:S1;
    	default: ns = IDLE;
    endcase
end

always@(posedge clk, negedge rst_n)begin
	if(!rst_n)begin
		valid_o <= 1'b0;
    end
    else begin
		case(ns)
			S3: valid_o <= 1'b1;
			default: valid_o <= 1'b0;
		endcase
    end

end

endmodule

②移位寄存器法

module sequence_detect_reg(
	input clk,
	input rst_n,
	input  data,
	output reg valid_o
);

reg[3:0] data_reg;

always@(posedge clk, negedge rst_n)begin
	if(!rst_n)begin
		data_reg <= 4'b0;
	end
	else begin
		data_reg <= {data_reg[2:0], data};
	end
end

always@(posedge clk, negedge rst_n)begin
	if(!rst_n)begin
		valid_o <= 1'b0;
	end
	else begin
		valid_o <= {data_reg[2:0], data}==4'b1001;
	end
end


endmodule