单bit跨时钟域（快到慢）

module fast_to_slow(
    clk_fast, clk_slow, rst_n, din, dout
);

input    clk_fast;
input    clk_slow;
input    rst_n;
input    din;
output   dout;

reg    pluse;
reg    pluse_r1;
reg    pluse_r2;
reg    pluse_r3;

//-------------------------------------------------
//脉冲展宽
//-------------------------------------------------
always@(posedge clk_fast or negedge rst_n)begin
    if(!rst_n)
        pluse <= 1'b0;
    else if(din)
            pluse <= ~pluse;
end

//-------------------------------------------------
//展宽的脉冲慢时钟域两级同步
//-------------------------------------------------
always@(posedge clk_slow or negedge rst_n)begin
    if(!rst_n)begin
        pluse_r1 <= 1'b0;
        pluse_r2 <= 1'b0;
        pluse_r3 <= 1'b0;
    end
    else begin
        pluse_r1 <= pluse;
        pluse_r2 <= pluse_r1;
        pluse_r3 <= pluse_r2;
    end
end

//-----------------------------------------------
//双边沿检测
//----------------------------------------------
assign dout = pluse_r3 ^ pluse_r2;

endmodule