AHB_SLAVE.V

最新推荐文章于 2024-05-06 10:41:42 发布

Jealky

最新推荐文章于 2024-05-06 10:41:42 发布

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分类专栏： AHB_SRAMC项目设计部分文章标签： verilog

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module ahb_if(
    //ahb_signals
    hclk,
    hrst_n,
    hsel,
    hwrite,
    hready,
    htrans,
    hburst,
    hsize,
    haddr,
    hwdata,
    hrdata,

    //sram_signal
    bank0_csn,
    bank1_csn,
    write_en,
    sram_addr,
    sram_wdata,
    sram_q0,
    sram_q1,
    sram_q2,
    sram_q3,
    sram_q4,
    sram_q5,
    sram_q6,
    sram_q7
    
);
input    hclk;
input    hrst_n;
input    hsel;
input    hwrite;
input    hready;
input[1:0]    htrans;
input[2:0]    hburst;
input[2:0]    hsize;
input[31:0]   haddr;
input[31:0]   hwdata;
output[31；0] hrdata； 

output[3:0]    bank0_csn;
output[3:0]    bank1_csn;
output         write_en;
output[12:0]    sram_addr;
output[7:0]     sram_wdata;
input[7:0]      sram_q0;
input[7:0]      sram_q1;
input[7:0]      sram_q2;
input[7:0]      sram_q3;
input[7:0]      sram_q4;
input[7:0]      sram_q5;
input[7:0]      sram_q6;
input[7:0]      sram_q7;

parameter    IDLE = 2'b00;
parameter    BUSY = 2'b01;
parameter    NONSEQ = 2'b10;
parameter    SEQ = 2'b11;

wire    bank_sel;
reg         hwrite_r;
reg[1:0]    htrans_r;
reg[2:0]    hburst_r;
reg[2:0]    hsize_r;
reg[31:0]   haddr_r;
reg[3:0]    bank_csn;

assign write_en = ((htrans_r == NONSEQ) || (htrans_r == SEQ)) && hwrite_r && hsel_r;
assign cs_n = !write_en;

assign bank_sel = haddr_r[15];
assign sram_addr = haddr_r[14:2];
assign sram_wdata = hwdata;
assign hrdata = bank_sel ? {sram_q7, sram_q6, sram_q5, sram_q4} : 
                           {sram_q3, sram_q2, sram_q1, sram_q0} ;
assign bank0_csn = (!cs_n && (bank_sel == 0)) ? bank_csn : 4'b1111;
assign bank1_csn = (!cs_n && (bank_sel == 1)) ? bank_csn : 4'b1111;

always@(posedge hclk or negedge rst_n)begin
    if(!hrst_n)begin
        hwrite_r <= 1'b0;
        htrans_r <= 2'b0;
        hburst_r <= 3'b0;
        hsize_r <= 3'b0;
        haddr_r <= 32'b0;
    end
    else if(hsel && hready)begin
            hwrite_r <= hwrite;
            htrans_r <= htrans;
            hburst_r <= hburst;
            hsize_r <= hsize;
            haddr_r <= haddr;
         end
end

always@(*)begin
   if(hszie_r == 3'b10)
        bank_csn = 4'b0000;
   else if(hsize_r == 3'b01)
            begin
                if(haddr[1] == 0)
                    bank_csn = 4'b1100;
                else
                    bank_csn = 4'b0011;
            end
        else if(hsize_r == 3'b00)
                begin
                    case(haddr[1:0])
                        2'b00:bank_csn = 4'b1110;
                        2'b01:bank_csn = 4'b1101;
                        2'b10:bank_csn = 4'b1011;
                        2'b11:bank_csn = 4'b0111;
                        default:bank_csn = 4'b1111;
                    endcase
                end
              else
                bank_csn = 4'b1111;
end

endmodule