Edgecapture

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0] in_last; //存储上次的值
    
    always @(posedge clk)
        begin
            in_last <= in;
        end

    always @(posedge clk)
        begin
            if(reset)
                out <= 0;
            else
                out <= (~in) & in_last |  out;  //检测下降沿
        end
endmodule

其中最后out <= (~in) & in_last | out比较厉害！