PT Training

转http://blog.sina.com.cn/s/blog_6f88b2c30100x0qz.html

# 要点 #

基本流程：
  Source Application Variable
  Read Netlist
  Link
  Read SDF
  Constrain
  Validate Constraints
  Initial Reports
  Save Session
  Quit

新增save session和restore_session命令（2004.12 version），必须版本一致。

1. Total Violation Reports
<report_analysis_coverage (= report_analysis)>
  部分参数：
   -status violated          报告所有的violations，按slack排列
   -check {setup hold}
   -sort_by slack/check_type  [Default: slack]

<report_constraint -all_violators(= -all)> 报告所有的violations，按clock domain排列

2. Specific Timing Reports
report_timing
报告解析（四部分）：
  1. Header.
    重点：
      Startpoint, Endpoint - 起止点，path的类型
      Group - 时钟域 Capture clock
      Type - max-setup, min-hold
  2. Data arrival.
    重点：
      clk edge - rise/fall
      delay - clock network(clk source latency + clk network latency),
              input, cell, net（r-rising, f-falling, *表示SDF信息）
      <report_timing -path full_clock  详细显示时钟路径>
      <report_timing -input_pins 详细显示路径中各单元的PIN，分别显示net delay和cell delay>
  3. Data required.
    重点：
      clk edge - setup/hold
      delay - clock network(clk source latency + clk network latency),
              output, clock skew
      library setup/hold time
  4. Slack.
    重点：
      slack - MET/VIOLATION
      required-arrival -> setup, -(required-arrival) -> hold
 
  Pre CTS: Ideal clocks
     Clock Uncertainty = Clock skew + Clock jitter [+ "Margin"]
  Post CTS: Propagated clocks
     Clock Uncertainty = Clock jitter [+ "Margin"]

<report_timing>
  Generates one report with the worst slack for each path group for setup time.
  即，默认报告每个group的setup的最差slack.
   部分参数：
     -max_paths  每个group报告的条数[默认为1]
     -nworst    每个endpoint报告的条数[默认为1]
       <report_timing -max_paths 4 -to FF1/D 结果只有1条，因为nworst=1>
     -group     指定path group
     -slack_lesser_than (= -slack_lesser) / -slack_greater_than
       <report_timing -slack_less 0  可以只查看violation的结果>
     -to / -rise_to / -fall_to [get_clocks CLK1]
     -from / -rise_from / -fall_from
     -through / -rise_through / -fall_through
     -exclude / -rise_exclude / -fall_exclude （2004.12的新命令）
     -nets      可以检查Fanout
     -significant_digits  数字的有效位数，默认3
       <set report_default_significant_digits 4  效果一样>
     -path      full_clock查看时钟路径；end只报告endpoint

A negative hold constraint imposes a positive hold requirement.

The transition at the data pin of the end point flip-flop affects the value of the library hold time. 即flip-flop数据D的fall/rise会影响library hold time.
  <report_timing -to FF2/D -delay max_fall>
  <report_timing -to FF2/D -delay min_fall>

Timing Arcs: Net delay, Cell delay, Flip-flop setup/hold
  类型：
  positive_unate, e.g. buffer
 negative_unate,     inv
  non_unate(positive_unate & negative_unate),  xor, xnor, mux, tri-state
 rising_edge,        clk->Q
 hold_clk_rise/setup_clk_rise, clk->D
   <report_lib -timing_arcs libraryname refname  查看对应单元的timing arc>

PS：给我们上课的PPMM似乎经验值不是很高，一开始忘了介绍自己，回答问题也不够肯定。

 

Day 2 执行流程

1. 建立Setup文件  .synopsys_pt.setup
   3个位置：
    (1) $SYNOPSYS/admin/setup  Standard Setup
    (2) ~user                 User's General Setup
    (3) project_dir           User's Specific Project Setup
    执行顺序：1->2->3 后覆盖前
   用途：
    定义变量
    alias
    suppress_message {...}
    source Tcl程序
      <foreach each_proc [glob -nocomplain ./tcl_procs/*.tcl] {source $each_proc}>

2. 建立运行脚本  RUN.tcl
   set search_path {...}
   lappend link_path tech_lib.db EEPROM_lib.db
   source ./scripts/variables.tcl
   read_verilog my_full_chip.v
   link_design MY_NAME
   read_sdf -analysis_type on_chip_variation name.sdf
    or:
    read_sdf -quiet -analysis_type bc_wc name.sdf
    redirect -append ./EW.log {report_annotated_delay; report_annotated_check}
    将反标信息写入文件EW.log 以便查看是否完全.
    bc_wc用于sdf文件里面包含2个差别很大条件下的min/max值.
      Setup check: Max delays for the data path & max delays for the clock path
      Hold  check: Min delays for the data path & Min delays for the clock path
    on_chip_variation用于sdf文件里面包含2个差别不大条件下的min/max值，一般比bc_wc更保守.
      Setup check: Max delays for the data path & Min delays for the clock path
      Hold  check: Min delays for the data path & Max delays for the clock path
   redirect -tee -append ./EW.log {print_message_info}
   redirect -tee -append ./EW.log {check_timing}
   redirect ./default_app_var {printvar -application}
   source -echo -verbose ./scripts/constraints.tcl
    or:
    set sh_source_emits_line_numbers W
    source ./scripts/constraints.tcl
    source默认quiet，即不显示
   redirect -tee -append ./EW.log {check_timing}
    check_timing -verbose
   redirect ./post_const_app_var {printvar -application}
  report_analysis_coverage
    redirect -tee -append ./RUN.sta {report_analysis_coverage}
   ...
   save_session -replace name_savesession

3. 其它
Never allow PT to create black boxes.
  set link_create_black_boxes false   default=true

set timing_update_status_level high   Timing updates时显示信息

不要用update_timing -full 耗时

==================================================================================
Day 3 时钟

1. 时钟
   3类时钟：Master clock, generated clock, virtual clock
  report_clock  查看时钟设置
  sizeof_collection [all_clocks] 时钟数目
  sizeof_collection [get_generated_clocks *] generated时钟数目
   report_timing -to sd_DQ[0] -path_type full_clock_expanded
    查看generated clock的source latency details(对virtual clock无效)
   check_timing -verbose -override clock_crossing检查时钟域的交叉
    or:
    lappend timing_check_defaults clock_crossing
    check_timing -verbose
  不是一个时钟域的路径，report_timing时会报告No constrained paths. 但若预先设置变量
    set timing_report_unconstrained_paths true 则可报告该路径.

  set_case_analysis 0 [get_ports {test_mode clk_sel}]
    Specify constant signals using case values
    <report_case_analysis>

   Identify all clock pins: all_registers -clock_pins
   Identify start point:   all_fanin -flat -startpoints -to <pin>
  
   检查多时钟:
    set timing_enable_multiple_clocks_per_reg false
    check_timing -override multiple_clock

  Path groups:
   default - virtual clock的path
   timing paths grouped by the capture clock
   **clock_gating_default** - 门控时钟
   **async_default** - 异步，复位 recovery/removal

2. SDF analysis type
  bc_wc, on_chip_variation
 
3. Additional checks
  Min pulse width checks
   <report_min_pulse_width -verbose I_ORCA_TOP/I_RISC_CORE/REG_FILE_B_RAM/CE2>
  Recovery and removal
   <report_timing -group ***async_default*>
  Latches and time borrow
  Multicycle paths
  Combinational feedback loops
   <set timing_dynamic_loop_breaking true>
  Non-unate cells in clock path

==================================================================================
参考：

Summary Reports for All Violations
 report_analysis_coverage   Total violations
   -status violated         Details on violations
   -check {setup hold}      For these timing checks
   -sort_by slack           Default
   -sort_by check_type
  report_constraint -all     Sort violations by clock group

report_timing   Switches: Control Which and How Many
 -nworst          Number of paths to consider per endpoint.
 -max_paths       Number of paths to generate per path group.
 -delay           Setup(max) or hold(min) with a specific end point data transition(max_rise, max_fall, min_rise, min_fall).
 -group           Focus on path group(e.g. capture clock name).
  -to -rise_to -fall_to
  -from -rise_from -fall_from
  -through -rise_through -fall_through
  -exclude -rise_exclude -fall_exclude
  -slack_lesser_than
  -slack_greater_than
 
report_timing   Switches: Control Details
 -input_pins      Show input pins and separate net and cell delays.
 -nets            Show net names and fanout.
 -derate          Show derate factor for each delay.
  -path full_clock Show cells on clock network for propagated clocks.
  -path short      Remove cells on data path.
  -path end        Report endpoint, data arrival, required and slack only.

Supporting Commands - Netlist Navigation and Debugging
  all_fanin -flat -start -to <pin>
  all_fanout -flat -end -from <pin>
  all_registers -level_sensitive -data_pins
  all_inputs -clock <clock>
  get_pins -of_objects <cell or net>
  all_connected <pin or net>
  report_cell -connections -verbose <cell>
  report_net -connections -verbose <net>
  report_lib -timing_arcs <lib> <lib_cell>
 
Helpful PrimeTime Commands
  restore_session <unix_dir>
  save_session -replace <unix_dir>
  report_timing -help
  help -verbose report_timing
  man report_timing
  help report*     Find commands
  printvar *sig*   Find variables
  list_libraries
  list_designs
  report_lib <lib_name>; #Time units
  remove_design -all
  remove_lib -all
  sh_list_key_bindings
  set sh_line_editing_mode emacs

# .synopsys_pt.setup
  alias page_on {set sh_enable_page_mode true}
  alias page_off {set sh_enable_page_mode false}
  alias un_on {set timing_report_unconstrained_paths true}
  alias un_off {set timing_report_unconstrained_paths false}
  suppress_message {ENV-003 PTSR-004 CMD-029}
  history keep 200
  set sh_enable_line_editing true
  foreach _file [glob -nocomplain ./tcl_procs/*.tcl] {source $_file}
 
# variables.tcl
  set report_default_significant_digits 4
  set link_create_black_boxes false
  set sh_source_uses_search_path true
  set sh_script_stop_severity E
  set timing_update_status_level high
 
Find Application Variables in the Constraints File
  redirect before.var {printvar -application}
  source -echo -verbose constraints.tcl
  redirect after.var {printvar -application}
  unix% diff after.var before.var
 
# RUN.Tcl
  set search_path {. ./scripts ./libs ./designs}
  lappend link_path mytech_lib.db RAM_lib.db
  source -echo -verbose ./scripts/variables.tcl
  read_verilog {top.v A.v B.v}
  link_design TOP
  read_sdf -quiet -analysis_type on_chip_variation top.sdf
  report_annotated_delay; report_annotated_check
  source -echo -verbose constraints.tcl
  redirect -tee ./EW.log {check_timing}
  report_analysis_coverage
  save_session -replace top_savesession
  redirect -tee -append ./EW.log {print_message_info}
  redirect -tee -append ./EW.log {quit}
 
Unix% pt_shell -f RUN.tcl | tee -i run.log

# Get to know the design clocks
  report_clock
  sizeof_collection [all_clocks]
  sizeof_collection [get_generated_clocks *]
  report_clock -skew MY_CLK; # Reports generated clock source latency
  report_timing -path full_clock_expanded; # Expands generated clock source latency
  check_timing -verbose -override clock_crossing
  set timing_all_clocks_propagated true; # Clocks created as propagated
# Identify clock network start points
  reset_design
  # Flay multiple clocks propagating (suggests a missing clock controlling signal)
  set timing_enable_multiple_clocks_per_reg false
  lappend timing_check_defaults ideal_clocks multiple_clock; # For check_timing
  report_case_analysis; # Report all case valuses set in design
 
# SDF and Analysis Types
  report_design; # Validate the analysis type
  set_annotated_delay
  remove_annotated_delay
  remove_annotated_check
  set_load; set_resistance; # Set net RC
  report_delay_calculation
  set timing_remove_clock_reconvergence_pessimism true
 
# Other
  report_timing -group **async_default**; #Recovery/Removal
  report_timing -group **clock_gating_default**
  report_clock_timing -type skew
  report_exceptions <-ignored>
  report_min_pulse_width
  report_timing -trace_latch_borrow