Verilog用计数器实现奇分频或偶分频

不管是奇分频还是偶分频，其实都是周期的倍增，所以只要用计数器计满倍增后一个时钟周期的个数（几分频就计几个数）

1.奇分频

是几分频计数器就计多少个数，然后posedge clk 产生一个中间变量（拉高一半加0.5个时钟周期），negedge clk 产生一个中间变量（拉高一半加0.5个时钟周期），错开半个时钟周期，让它们逻辑相与（拉高一半减0.5个时钟周期时是逻辑相或）

module div_5 (
    input clk,
    input rstn,

    output wire div5
);
    reg X;

    reg Y;

    reg [4:0] cnt_1;

    always @(posedge clk or negedge rstn) begin
        if (rstn == 1'b0) begin
            cnt_1 <= 5'd0;
        end
        else if (cnt_1 == 5'd4) begin
            cnt_1 <= 5'd0;
        end
        else begin
            cnt_1 <= cnt_1 + 5'd1;

        end
    end

    always @(posedge clk or negedge rstn) begin
        if (rstn == 1'b0) begin
            X <= 1'b0;
        end
        else if (cnt_1 >= 5'd1 && cnt_1 <= 5'd3 ) begin
            X <= 1'b1;
        end
        else begin
            X <= 1'b0;
        end
    end


    always @(negedge clk or negedge rstn) begin
        if (rstn == 1'b0) begin
            Y <= 1'b0;
        end
        else if (cnt_1 >= 5'd1 && cnt_1 <= 5'd3 ) begin
            Y <= 1'b1;
        end
        else begin
            Y <= 1'b0;
        end
    end

assign div5 = X && Y;


endmodule

`timescale 1ns/1ps

module div_5_tb ();
    reg clk;
    reg rstn;

    wire div5;
    
    initial begin
        clk = 1'b0;
        rstn = 1'b0;
        #50
        rstn = 1'b1;

    end

    always #10 clk = ~clk;

div_5 div_5 (

    .clk(clk),
    .rstn(rstn),

    .div5(div5)

);   


endmodule

2.偶分频

是几分频计数器就计多少个数，然后记到一半时取反，然后在另外一个always块里赋值，比如四分频

module div_4 (
    input clk,
    input rstn,

    output reg div4
);

   reg [3:0] cnt;

   always @(posedge clk or negedge rstn) begin
    if (rstn == 1'b0) begin
        cnt <= 4'd0;
    end
    else if (cnt == 4'd3) begin
        cnt <= 4'd0;
    end
    else begin
        cnt <= cnt + 4'd1;
    end
   end


   always @(posedge clk or negedge rstn) begin
    if (rstn == 1'b0) begin
        div4 <= 1'b0;
    end
    else if (cnt >= 4'd2 && cnt <= 4'd3) begin
        div4 <= 1'b1;
    end
    else begin
        div4 <= 1'b0;
    end
   end

endmodule

`timescale 1ns/1ps

module div_4_tb ();
    reg clk;
    reg rstn;

    wire div4;

    initial begin
        clk = 1'b0;
        rstn = 1'b0;
        #50
        rstn = 1'b1;

    end

    always #10 clk = ~clk;

div_4 div_4 (

    .clk(clk),
    .rstn(rstn),

    .div4(div4)

);
endmodule