【verilog学习19】HDLBits：Circuits_Sequential Logic_Shift Registers

I Four-bit Shift Register (Shift4)

1.代码编写

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 

    always@(posedge clk , posedge areset) begin
        if(areset) 
            q <= 4'b0000;
        else if(load)
            q <= data;
        else if(ena)begin
           // integer i;
           // for(i=1;i<=4;i++) begin
           //    q <= {0,q[3:i]};
           // end
            q <= (q >> 1);
        end
        else
            q <= q;
    end
endmodule

2.提交结果

Success

3.题目分析

Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable.

• areset: Resets shift register to zero.
• load: Loads shift register with data[3:0] instead of shifting.
• ena: Shift right (q[3] becomes zero, q[0] is shifted out and disappears).
• q: The contents of the shift register.
  If both the load and ena inputs are asserted (1), the load input has higher priority.
  实现逻辑右移。

$算数右移、逻辑右移、循环右移，算数/逻辑左移：$
$算数右移：整体右移（包括符号位），高位补符号位。$
$逻辑右移：整体右移，高位补0（q>>1）。$
$循环右移：整体右移，将最低位补到最高位。$
$算数/逻辑左移：算术左移等同于逻辑左移。$

II Left/Right rotator

1.代码编写

module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q); 
    always@(posedge clk) begin
        if(load)
            q <= data;
        else begin
            case(ena)
                2'b10: q <= {q[98:0],q[99]};
                2'b01: q <= {q[0],q[99:1]};
                default: q <= q;
            endcase
        end
    end
endmodule

2.提交结果

Success

3.题目分析

Build a 100-bit left/right rotator, with synchronous load and left/right enable. A rotator shifts-in the shifted-out bit from the other end of the register, unlike a shifter that discards the shifted-out bit and shifts in a zero. If enabled, a rotator rotates the bits around and does not modify/discard them.

• load: Loads shift register with data[99:0] instead of rotating.
• ena[1:0]: Chooses whether and which direction to rotate.
  2’b01 rotates right by one bit
  2’b10 rotates left by one bit
  2’b00 and 2’b11 do not rotate.
• q: The contents of the rotator.
  （每个上升沿挪一次，不用for）

III Left/Right arithmetic shift by 1 or 8

1.代码编写

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
    always@(posedge clk) begin
        if(load)
            q <= data;
        else begin
            case({ena,amount})
                3'b100: q <= {q[62:0],1'b0};               
                3'b101: q <= {q[55:0],8'b0};
                3'b110: q <= {q[63],q[63:1]};
                3'b111: q <= {{8{q[63]}},q[63:8]};
                default: q <= q;
            endcase
        end
    end
endmodule

2.提交结果

Success

3.题目分析

Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.

An arithmetic right shift shifts in the sign bit of the number in the shift register (q[63] in this case) instead of zero as done by a logical right shift. Another way of thinking about an arithmetic right shift is that it assumes the number being shifted is signed and preserves the sign, so that arithmetic right shift divides a signed number by a power of two.

There is no difference between logical and arithmetic left shifts.

• load: Loads shift register with data[63:0] instead of shifting.
• ena: Chooses whether to shift.
• amount: Chooses which direction and how much to shift.
  2’b00: shift left by 1 bit.
  2’b01: shift left by 8 bits.
  2’b10: shift right by 1 bit.
  2’b11: shift right by 8 bits.
• q: The contents of the shifter.
  $复习：复制$
  q < = { { 8 { q [ 63 ] } } , q [ 55 : 0 ] } q <= \color{red}\left\{\color{LimeGreen}\left\{\color{Black}8\color{Pink}\left\{\color{Black}q[63]\color{pink}\right\}\color{LimeGreen}\right\}\color{black},q[55:0]\color{red}\right\} q<={{8{q[63]}},q[55:0]}
  最内侧$粉色$花括号:8{q[63]}表示复制q[63] 8次。
  中间$绿色$花括号：将复制产生的8个q[63]组合起来。
  最外侧$红色$花括号：再与q[55:0]相组合，形成64位的输出vector。

IV 5-bit LFSR (Lfsr5)

1.代码编写

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 
    always@(posedge clk) begin
        if(reset)
            q <= 5'h1;
        else begin
            q[4] <= 1'h0^q[0];
            q[3] <= q[4];
            q[2] <= q[3]^q[0];
            q[1] <= q[2];
            q[0] <= q[1];
        end
    end
endmodule

2.提交结果

Success

3.题目分析

A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a “tap” are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps positions are carefully chosen, the LFSR can be made to be “maximum-length”. A maximum-length LFSR of n bits cycles through 2n-1 states before repeating (the all-zero state is never reached).

The following diagram shows a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3. (Tap positions are usually numbered starting from 1). Note that I drew the XOR gate at position 5 for consistency, but one of the XOR gate inputs is 0.

Build this LFSR. The reset should reset the LFSR to 1.

• 关于LFSR（线性反馈移位寄存器）

https://zhuanlan.zhihu.com/p/366067972
就是反馈移位寄存器某些位（抽头）进行异或。

V 3-bit LFSR (Mt2015 lfsr)

1.代码编写

module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output [2:0] LEDR);  // Q
    wire [2:0] rout;
    always@(*) begin
    case(KEY[1])
        1'h1: rout = SW;
        1'h0: rout = {LEDR[2]^LEDR[1],LEDR[0],LEDR[2]};
    endcase
    end
    always@(posedge KEY[0]) begin
        LEDR <= rout;
    end
endmodule

2.提交结果

Success

3.题目分析

Taken from 2015 midterm question 5. See also the first part of this question: mt2015_muxdff

Write the Verilog code for this sequential circuit (Submodules are ok, but the top-level must be named top_module). Assume that you are going to implement the circuit on the DE1-SoC board. Connect the R inputs to the SW switches, connect Clock to KEY[0], and L to KEY[1]. Connect the Q outputs to the red lights LEDR.
组合逻辑，时序逻辑过程块。

VI 32-bit LFSR (Lfsr32)

1.代码编写

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 32'h1
    output [31:0] q
); 
    always@(posedge clk) begin
        if(reset) q <= 32'h1;
        else begin
            q[31] <= 1'h0^q[0];
            q[21] <= q[22]^q[0];
            q[1] <= q[0]^q[2];
            q[0] <= q[0]^q[1];
            {q[30:22],q[20:2]} <= {q[31:23],q[21:3]};
        end
    end
endmodule

2.提交结果

Success

3.题目分析

See Lfsr5 for explanations.
Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1.
Hint:This is long enough that you’d want to use vectors, not 32 instantiations of DFFs.

VII Shift Register (Exams/m2014 q4k)

1.代码编写

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    wire [3:0] q;
    always@(posedge clk) begin
        if(~resetn) q <= 4'h0;
        else q <= {in,q[3:1]};        
        //out <= q[0]; 不能这么写，这相当于在q[0]和out间又加了一个寄存器
    end
    assign out = q[0];
endmodule

2.提交结果

Success

3.题目分析

Implement the following circuit:
对电路进行综合

out和q[0]之间直接连接，所以用连续赋值。
注意这里是resetn，低电平置位（看图）。

VIII Shift Register (Exams/2014 q4b)

1.代码编写

module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
); //
    MUXDFF instance1(.e(KEY[1]),.r(SW[3]),.L(KEY[2]),.w(KEY[3]),.clk(KEY[0]),.q(LEDR[3]));
    MUXDFF instance2(.e(KEY[1]),.r(SW[2]),.L(KEY[2]),.w(LEDR[3]),.clk(KEY[0]),.q(LEDR[2]));
    MUXDFF instance3(.e(KEY[1]),.r(SW[1]),.L(KEY[2]),.w(LEDR[2]),.clk(KEY[0]),.q(LEDR[1]));
    MUXDFF instance4(.e(KEY[1]),.r(SW[0]),.L(KEY[2]),.w(LEDR[1]),.clk(KEY[0]),.q(LEDR[0]));
endmodule

module MUXDFF (
	input e,
	input r,
	input L,
	input w,
	input clk,
	output q);
    wire muxout;
    always@(*) begin
        case({e,L})
            2'b00: muxout = q;
            2'b01: muxout = r;
            2'b11: muxout = r;
            2'b10: muxout = w;
        endcase
    end
    always@(posedge clk) begin
        q <= muxout;
    end
endmodule

2.提交结果

Success

3.题目分析

Consider the n-bit shift register circuit shown below:

Write a top-level Verilog module (named top_module) for the shift register, assuming that n = 4. Instantiate four copies of your MUXDFF subcircuit in your top-level module. Assume that you are going to implement the circuit on the DE2 board.

Connect the R inputs to the SW switches,
clk to KEY[0],
E to KEY[1],
L to KEY[2], and
w to KEY[3].
Connect the outputs to the red lights LEDR[3:0].
(Reuse your MUXDFF from exams/2014_q4a.)
实例化。

IV 3-input LUT (Exams/ece241 2013 q12)

1.代码编写

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 
    reg[0:7] Q;
    always@(*) begin
        case({A,B,C})
            3'h0: Z = Q[0];
            3'h1: Z = Q[1];
            3'h2: Z = Q[2];
            3'h3: Z = Q[3];
            3'h4: Z = Q[4];
            3'h5: Z = Q[5];
            3'h6: Z = Q[6];
            3'h7: Z = Q[7];
        endcase
    end
    always@(posedge clk) begin
        if(enable) 
            Q <= {S,Q[0:6]};
        else
            Q <= Q;
    end
endmodule

2.提交结果

Success

3.题目分析

In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is “random access”, as in a typical RAM. You will then use the circuit to realize a 3-input logic function.

First, create an 8-bit shift register with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]…Q[7]. The shift register input should be called S, which feeds the input of Q[0] (MSB is shifted in first). The enable input controls whether to shift. Then, extend the circuit to have 3 additional inputs A,B,C and an output Z. The circuit’s behaviour should be as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so on. Your circuit should contain ONLY the 8-bit shift register, and multiplexers. (Aside: this circuit is called a 3-input look-up-table (LUT)).
就是一个ShiftRegister与MUX组合。