HDLbits---Verilog language ---more Verilog features

1.Conditional

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//

    // assign intermediate_result1 = compare? true: false;
    wire [7:0] x ,y;
    assign x=(a<b)?a:b;
    assign y=(c<d)?c:d;
    assign min=(x<y)?x:y;
endmodule

2.Reduction

module top_module (
    input [7:0] in,
    output parity); 
 
assign parity = ^in;
endmodule

3.Gates100

module top_module( 
    input [99:0] in,
    output out_and,
    output out_or,
    output out_xor 
);
assign out_and=∈
    assign out_or=|in;
    assign out_xor=^in;
endmodule

4.Vector100r

module top_module( 
    input [99:0] in,
    output [99:0] out
);
integer i;
    always@(*)
    for(i=0;i<100;i++)
         out[i]=in[99-i];
endmodule

5.Popcount255

module top_module( 
    input [254:0] in,
    output [7:0] out );
    reg[7:0] a;
    
integer i;
    always@(*) begin
         a=0;
        
        for(i=0;i<255;i++)
            a=(in[i]==1)?a+1:a;
    end
    assign out=a;
endmodule

6.Adder100i

module top_module( 
    input  [99:0]  a, b,
    input          cin,
    output [99:0]  cout,
    output [99:0]  sum 
);
    genvar i;
    generate
        for(i=0;i<100;i=i+1) begin:adder
            if(i==0)
                assign{cout[0],sum[0]}=a[0]+b[0]+cin;
            else
                assign{cout[i],sum[i]}=a[i]+b[i]+cout[i-1];
        end           
    endgenerate
    
endmodule

7.Bcdadd100

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
reg [99:0] cout_reg;
bcd_fadd (
            .a(a[3:0]),
            .b(b[3:0]),
            .cin(cin),
            .cout(cout_reg[0]),
            .sum(sum[3:0])
        );

genvar i;
generate
    for (i = 1;i<=99 ; i=i+1) begin:fadd
        bcd_fadd fadd(
            .a(a[4*(i+1)-1:4*(i+1)-4]),
            .b(b[4*(i+1)-1:4*(i+1)-4]),
            .cin(cout_reg[i-1]),
            .cout(cout_reg[i]),
            .sum(sum[4*(i+1)-1:4*(i+1)-4])
        );
    end
endgenerate
assign cout = cout_reg[99];
endmodule