FPGA中分频电路设计

偶分频，N为需要分频的倍数

parameter N = 32;                  //分频倍数
parameter CLK_DIVDER_MAX = N/2;

reg clk_divder;
reg [4:0] cnt_divder;

always@(posedge clk or negedge rst)
    if(!rst)
    cnt_divder <= 1'b0;
    else if(cnt_750 == CLK_DIVDER_MAX - 1)
    cnt_divder <= 1'b0;
    else
    cnt_divder <= cnt_divder + 1'd1;

always@(posedge clk or negedge rst)
    if(!rst)
    clk_divder <= 1'b0;
    else if(cnt_750 == 4'd15)
    clk_divder <= ~clk_divder;
    else
    clk_divder <= clk_divder;

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