Verilog 练习 计数器

 代码如下

//2021-11-2
//计数器；
module counter(clk,res,y);
input clk,res;
output[7:0] y;

reg[7:0] y;
//wire[7:0] sum;
//assign sum=y+1;

always@(posedge clk or negedge res)
if(~res) y=0;
else y=y+1; //y=sum;


endmodule


//----testbench of counter----
module counter_tb;
reg clk,res;
wire[7:0] y;

counter counter(.clk(clk),.res(res),.y(y));

initial begin
		clk<=0;res<=0;
		#17  res<=1;
		#6000 $stop;
end 

always#5 clk<=~clk;

endmodule

仿真结果如下

 

https://www.bilibili.com/video/BV1hX4y137Ph?p=4&spm_id_from=pageDriver