HDLBits练习——Exams/m2014 q4c

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.

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前言

三个输入，包括一个时钟clk，一个高电平有效的同步置位信号resetn，一个使能控制信号slowena；一个输出信号q。

代码

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);
    always@(posedge clk)begin
        if(reset) q<=4'd0;
        else if(q<4'd9) q<=slowena?(q+1'b1):q;
        else if(q==4'd9) q<=slowena?4'd0:q;
        else q<=4'd0;
    end
endmodule

总结

放慢计数节奏，slowena是放慢的使能信号，刚开始的时候没考虑到else if(q==4’d9) q<=slowena?4’d0:q;这种情况，出现了错误，因此对于计数节奏放慢而言，slowena信号不仅控制正常计数的节奏，还控制了循环的节奏，一定要注意。