module odd_divclk #(
parameter DIV = 5 ,
parameter DIV_WIDTH = 3
)(
input clk_in ,
input rst_n ,
output clk_out
);
reg [DIV_WIDTH - 1:0] cnt_p = 0;
reg [DIV_WIDTH - 1:0] cnt_n = 0;
reg clk_p = 0;
reg clk_n = 0;
always @ (posedge clk_in or negedge rst_n)
if(!rst_n)
cnt_p <= 0;
else if(cnt_p < DIV - 1)
cnt_p <= cnt_p + 1'b1;
else
cnt_p <= 0;
always @ (negedge clk_in or negedge rst_n)
if(!rst_n)
cnt_n <= 0;
else if(cnt_n < DIV - 1)
cnt_n <= cnt_n + 1'b1;
else
cnt_n <= 0;
always @ (posedge clk_in or negedge rst_n)
if(!rst_n)
clk_p <= 1'b0;
else if((cnt_p == ((DIV - 1)>>1)) || (cnt_p == DIV - 1))
clk_p <= ~clk_p;
always @ (negedge clk_in or negedge rst_n)
if(!rst_n)
clk_n <= 1'b0;
else if((cnt_n == ((DIV - 1)>>1)) || (cnt_n == DIV - 1))
clk_n <= ~clk_n;
assign clk_out = clk_p | clk_n;
endmodule```
占空比50%,任意奇数分频模块
于 2021-07-26 16:52:20 首次发布
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