FPGA任意奇偶数分频占空比50%

简单的是计数取反，奇数略有不同，分为上升沿和下降沿计数取反然后再逻辑与即可，相当于补了半个周期

module PulseDiv(input clk_100M,input n_rst,output reg pulseout);

reg[7:0] divcnt;
reg clkp,clkn;

//任意偶数分频占空比50% 10分频
always@(posedge clk_100M or negedge n_rst)
begin
    if(!n_rst)
    begin
        divcnt <= 8'd0;
        pulseout <= 1'd0;
    end
    else
    begin
        if(divcnt == 8'd4)
        begin
            divcnt <= 8'd0;
            pulseout <= ~pulseout;
        end
        else
        begin
            divcnt <= divcnt + 8'd1;
        end
    end
end

//任意奇数分频占空比(50%+1/N) 11分频
always@(posedge clk_100M or negedge n_rst)
begin
    if(!n_rst)
    begin
        divcnt <= 8'd0;
        pulseout <= 1'd0;
    end
    else
    begin
        if(divcnt == 8'd4)
        begin
            divcnt <= divcnt + 8'd1;
            pulseout <= 1'd1;
        end
        else
        begin
            if(divcnt == 8'd10)
            begin
                divcnt <= 8'd0;
                pulseout <= 1'd0;
            end
            else
            begin
                divcnt <= divcnt + 8'd1;
            end
        end
    end
end

//任意奇数分频占空比50% 11分频
always@(posedge clk_100M or negedge n_rst)
begin
    if(!n_rst)
    begin
        divcnt <= 8'd0;
        clkp <= 1'd0;
    end
    else
    begin
        if(divcnt == 8'd4)
        begin
            divcnt <= divcnt + 8'd1;
            clkp <= 1'd1;
        end
        else
        begin
            if(divcnt == 8'd10)
            begin
                divcnt <= 8'd0;
                clkp <= 1'd0;
            end
            else
            begin
                divcnt <= divcnt + 8'd1;
            end
        end
    end 
end

always@(posedge clk_100M or negedge n_rst)
begin
    if(!n_rst)
    begin
        divcnt <= 8'd0;
        clkn <= 1'd0;
    end
    else
    begin
        if(divcnt == 8'd4)
        begin
            divcnt <= divcnt + 8'd1;
            clkn <= 1'd1;
        end
        else
        begin
            if(divcnt == 8'd10)
            begin
                divcnt <= 8'd0;
                clkn <= 1'd0;
            end
            else
            begin
                divcnt <= divcnt + 8'd1;
            end
        end
    end 
end

assign pulseout = clkp & clkn;//将pulseout改为wire再运行
endmodule