占空比50%的奇数分频

占空比50%的奇数分频

题目描述
设计一个同时输出7分频的时钟分频器，占空比要求为50%
注意rst为低电平复位。

信号示意图：

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
    reg[3:0]count_1; reg[3:0]count_2; reg[1:0] data;
always @(posedge clk_in or negedge rst)
    if (!rst)begin
        count_1 <= 0;
        count_2 <= 0;
        data <= 0;
    end
else
    count_1 <= count_1 + 1;

always @(negedge clk_in or negedge rst)
    if (!rst)begin
        count_1 <= 0;
        count_2 <= 0;
        data <= 0;
    end
else
    count_2 <= count_2 + 1;

always @(*)begin
    if(count_1+count_2 == 7)begin
        count_1 = 0;
        count_2 = 0;
        data = ~data;
    end
    else 
      
        data = data;
    
end

assign clk_out7 = data;

//*************code***********//

endmodule