异步复位同步释放的VHDL实现代码

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    03:21:20 10/08/2019 
-- Design Name: 
-- Module Name:    Syn_Asyn_Reset - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Syn_Asyn_Reset is
    Port ( clk : in  STD_LOGIC;
           rst_n : in  STD_LOGIC;
           data_in : in  STD_LOGIC;
           data_out : out  STD_LOGIC);
end Syn_Asyn_Reset;

architecture Behavioral of Syn_Asyn_Reset is

    signal rst_n_inter, data_inter:std_logic;

begin
process(clk)
begin
    if(clk'event and clk='1') then
        rst_n_inter<=rst_n;
    end if;
end process;

process(clk,rst_n_inter)
begin
    if(rst_n_inter='0') then 
        data_out<='0';
        data_inter<='0';
   elsif(clk'event and clk='1') then
        data_out<=data_inter;
        data_inter<=data_in;
    end if;    
end process;

end Behavioral;