极简UVM RAL示例(PART3--后门访问，PART4--内建ral sequence)

最新推荐文章于 2023-12-14 16:12:21 发布

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最新推荐文章于 2023-12-14 16:12:21 发布

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本文链接：https://blog.csdn.net/zt5169/article/details/126562504

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本文介绍如何在RTL级验证中实现RAL后门访问，并通过修改测试代码进行后门路径、默认值及读写访问的序列检查。针对后门访问，文章详细展示了如何在不同阶段进行读写操作；对于序列测试，包括了后门路径的有效性验证、默认值的校验以及读写操作的正确性检查。

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基于part2，修改支持ral 后门仿问

tests代码

第一处修改build_phase

rgm.reset();
rgm.set_hdl_path_root("tb_top.u_dut");

第二处修改main_phase

//backdoor
rgm.reg2_reg.write(status,'h20,UVM_BACKDOOR);
rgm.reg2_reg.read(status,value,UVM_FRONTDOOR);
`uvm_info(get_full_name(),$sformatf("frontdoor read %s:%0h",rgm.reg2_reg.get_full_name(),value),UVM_MEDIUM);
rgm.reg2_reg.read(status,value,UVM_BACKDOOR);
`uvm_info(get_full_name(),$sformatf("backdoor read  %s:%0h",rgm.reg2_reg.get_full_name(),value),UVM_MEDIUM);
rgm.reg2_reg.read(status,value,UVM_FRONTDOOR);
`uvm_info(get_full_name(),$sformatf("frontdoor read %s:%0h",rgm.reg2_reg.get_full_name(),value),UVM_MEDIUM);
rgm.reg2_reg.peek(status,value);
`uvm_info(get_full_name(),$sformatf("backdoor peek  %s:%0h",rgm.reg2_reg.get_full_name(),value),UVM_MEDIUM);
rgm.reg2_reg.read(status,value,UVM_FRONTDOOR);
`uvm_info(get_full_name(),$sformatf("frontdoor read %s:%0h",rgm.reg2_reg.get_full_name(),value),UVM_MEDIUM);

基于part3，还可以实验内建ral序列

1）检查后门路径的序列

修改tests的main_phase

uvm_reg_mem_hdl_paths_seq chk_bkdoor;
phase.raise_objection(this);
chk_bkdoor =new("chk_bkdoor");
chk_bkdoor.model = rgm;
chk_bkdoor.start(null);

检查结果

UVM_INFO /home/eda_tool/vcs-mx/O-2018-09-SP2-1/vcs-mx/O-2018.09-SP2-1/etc/uvm/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh(70) @ 0: reporter@@chk_bkdoor [uvm_reg_mem_hdl_paths_seq] checking HDL paths for all registers/memories in rgm
UVM_INFO /home/eda_tool/vcs-mx/O-2018-09-SP2-1/vcs-mx/O-2018.09-SP2-1/etc/uvm/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh(97) @ 0: reporter@@chk_bkdoor [uvm_reg_mem_hdl_paths_seq] Validating HDL paths in rgm for default design abstraction
UVM_INFO /home/eda_tool/vcs-mx/O-2018-09-SP2-1/vcs-mx/O-2018.09-SP2-1/etc/uvm/reg/sequences/uvm_reg_mem_hdl_paths_seq.svh(81) @ 0: reporter@@chk_bkdoor [uvm_reg_mem_hdl_paths_seq] HDL path validation completed

2）检查默认值的序列

修改tests的main_phase

uvm_reg_hw_reset_seq chk_default;
phase.raise_objection(this);
chk_default = new("chk_default");
chk_default.model = rgm;
chk_default.start(null);

检查结果

Starting chk_default sequence…

UVM_INFO /home/eda_tool/vcs-mx/O-2018-09-SP2-1/vcs-mx/O-2018.09-SP2-1/etc/uvm/reg/sequences/uvm_reg_hw_reset_seq.svh(148) @ 0: reporter@@chk_default [uvm_reg_hw_reset_seq] Verifying reset value of register rgm.reg1_reg in map “rgm.uvm_reg_map”…
Verdi Enable Verdi Recorder.
Info: Verdi UVM 1.1d Hooks File 07/11/2013
UVM_INFO /home/eda_tool/vcs-mx/O-2018-09-SP2-1/vcs-mx/O-2018.09-SP2-1/etc/uvm/reg/sequences/uvm_reg_hw_reset_seq.svh(148) @ 15000: reporter@@chk_default [uvm_reg_hw_reset_seq] Verifying reset value of register rgm**.reg2_reg** in map “rgm.uvm_reg_map”…
UVM_INFO /home/eda_tool/vcs-mx/O-2018-09-SP2-1/vcs-mx/O-2018.09-SP2-1/etc/uvm/reg/sequences/uvm_reg_hw_reset_seq.svh(148) @ 21000: reporter@@chk_default [uvm_reg_hw_reset_seq] Verifying reset value of register rgm.reg3_reg in map “rgm.uvm_reg_map”…
UVM_ERROR /home/eda_tool/vcs-mx/O-2018-09-SP2-1/vcs-mx/O-2018.09-SP2-1/etc/uvm/reg/uvm_reg.svh(2929) @ 27000: reporter [RegModel] Register “rgm**.reg3_reg**” value read from DUT (0x0000000000000001) does not match mirrored value (0x0000000000000000)
UVM_INFO /home/eda_tool/vcs-mx/O-2018-09-SP2-1/vcs-mx/O-2018.09-SP2-1/etc/uvm/reg/sequences/uvm_reg_hw_reset_seq.svh(148) @ 27000: reporter@@chk_default [uvm_reg_hw_reset_seq] Verifying reset value of register rgm.reg4_reg in map “rgm.uvm_reg_map”…

问题分析：检查默认值时，reg3的镜像值来自 reg3.configure()。所以，可以修改reg3的初始配置值。

3）检查读写的序列

修改tests的main_phase

uvm_reg_hw_reset_seq chk_default;
phase.raise_objection(this);
chk_default = new("chk_default");
chk_default.model = rgm;
chk_default.start(null);

检查结果

Starting chk_access sequence…

UVM_WARNING /home/eda_tool/vcs-mx/O-2018-09-SP2-1/vcs-mx/O-2018.09-SP2-1/etc/uvm/reg/sequences/uvm_reg_access_seq.svh(110) @ 33000: reporter@@chk_access.single_reg_access_seq [uvm_reg_access_seq] Register ‘rgm.reg1_reg’ has RO fields
UVM_INFO /home/eda_tool/vcs-mx/O-2018-09-SP2-1/vcs-mx/O-2018.09-SP2-1/etc/uvm/reg/sequences/uvm_reg_access_seq.svh(145) @ 33000: reporter@@chk_access.single_reg_access_seq [uvm_reg_access_seq] Verifying access of register ‘rgm.reg2_reg’ in map ‘rgm.uvm_reg_map’ …
UVM_INFO /home/eda_tool/vcs-mx/O-2018-09-SP2-1/vcs-mx/O-2018.09-SP2-1/etc/uvm/reg/sequences/uvm_reg_access_seq.svh(145) @ 45000: reporter@@chk_access.single_reg_access_seq [uvm_reg_access_seq] Verifying access of register ‘rgm.reg3_reg’ in map ‘rgm.uvm_reg_map’ …
UVM_ERROR /home/eda_tool/vcs-mx/O-2018-09-SP2-1/vcs-mx/O-2018.09-SP2-1/etc/uvm/reg/uvm_reg.svh(2929) @ 51100: reporter [RegModel] Register “rgm.reg3_reg” value read from DUT (0x0000000000000001) does not match mirrored value (0x0000000000000000)
UVM_INFO /home/eda_tool/vcs-mx/O-2018-09-SP2-1/vcs-mx/O-2018.09-SP2-1/etc/uvm/reg/sequences/uvm_reg_access_seq.svh(145) @ 57000: reporter@@chk_access.single_reg_access_seq [uvm_reg_access_seq] Verifying access of register ‘rgm.reg4_reg’ in map ‘rgm.uvm_reg_map’ …
UVM_ERROR /home/eda_tool/vcs-mx/O-2018-09-SP2-1/vcs-mx/O-2018.09-SP2-1/etc/uvm/reg/uvm_reg.svh(2929) @ 63100: reporter [RegModel] Register “rgm.reg4_reg” value read from DUT (0x000000000000ffff) does not match mirrored value (0x0000000000000000)