Verilog出现错误总结

1
错误：Error (10200): Verilog HDL Conditional Statement error at key_led.v(13): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
代码：

always @ (negedge clk or posedge rst_n) begin    //错误出现在此处
    if(!rst_n)
        cnt <= 24'd0;
    else if(cnt < 24'd9_999_999)
        cnt <= cnt + 1'b1;
    else
        cnt <= 0;
end 

解决：
问题出现在把复位信号设置成上升触发，而后又判断是否为低电平。将其改成：

always @ (posedge clk or negedge rst_n) begin   
    if(!rst_n)
        cnt <= 24'd0;
    else if(cnt < 24'd9_999_999)
        cnt <= cnt + 1'b1;
    else
        cnt <= 0;
end