A work not, this blog is about the past month’s knowledge points summary.
Linux Terminal
- Environment configuration file: In the source directory input
source .cshrc_my
and theng .cshrc_my
or direct input commandg ~/.cshrc_my
( g:gvim,cause the file write this sentence:alias g gvim
that means use command “g” instead of “gvim”, suchlike:
alias vi vim
alias gd gvim -d(gd means compare two files)
alias h history
)
- VIM configuration file: In the source directory input
g .vimrc
- Delete folder:
rm -rf filename/
- Delete file:
rm -f filename/
- Delete a certain type of file: e.g:
rm *.fsdb
(delete .fsdbtype file) orrm debug_0*
(Delete files which filenames start with debug 0) - Delete link file:
rm -rf filename
- link file: e.g:
ln -s /var/test test
(The current path to create test folder link to /var/test folder) - Alter link file:
ln -snf /newfile test
- New directory:
mkdir filename/
- Copy file:
cp /path/filename . -r
- Generate workbench:
gnr iS.wb
(On condition that have a kind of environment include Tcl file such as iSSIM.log) - Terminate the command: ctrl + c
- To suspend the order: ctrl + z
- Search file: e.g:
ll *.fsdb
- Decompressing ZIP file:
unzip filename.zip -d filename
- Linux命令大全
GVIM
-
One file into other file: move the cursor to the filename, and then strike gf
-
Return last file: ctrl + shift + o
-
Enter edit pattern:
Press i、I、a、A、o、O、r、R one of keys
when enter edit pattern, at the bottom of the screen will show INSERT or REPLACE.
From edit pattern come back normal mode, press Esc.
i: Insert before the current character
I: Insert at the beginning of the line where the cursor is located
a: Insert after the current character
A: Insert at the end of the line where the cursor is located -
Command mode:
press the key:
or/
In this mode, you can search character or string, also can save, replace, exit, display line number and so on.
:w
save text.
:q
exit vim.
:w!
Mandatory saving.
:q!
Forced exit, all changes do not take effect.
:wq
saving and exit.
:set nu
diaplay line numbers.
q:
VIM’s history commands window.
/word
Find a string ofword
after the cursor, press n backward to continue the search, shift+n upward search.
:n1,n2s/word1/word2/g
Look up word1 between the n1 and n2 lines and replace it with word2, if don’t addg
then only replace the first word1 of each line.(The order is start point-> , ->end point-> s (means replace) -> need replace word ->has been replaced word-> g(means all) )
:1,$s/word1/word2/g
Replace all word1 in the document with word2, $ means to the end.
Verdi
So far, it’s only used to check .fsdb waveform, debug, source RTL code after simulation in a simple simulation environment.
- Open verdi: In syn/ directory input command
./gen_fpga_vflie &
orrun_verdi
- Drive: The concept is similar to where does the output signal come from
- Load: The concept is similar to where does the input signal go
- 一个对以后有用的Verdi链接(关于irun)
- Verdi使用教程(较全)
Synplify
Comprehensive tools, see the user manual for use.
Verilog
- Dunmp function:
Verilog provides a series of system tasks for recording changes in signal values. Common formats include VCD, FSDB, etc.
Dump VCD format
$dumpfile("file. dump"); //打开一个VCD数据库用于记录
$dumpvars(level,start_module); //要记录的信号,level=0表示记录所有
$dumpflush; //将VCD数据保存到磁盘 不明白
$dumpoff; //停止记录
$dumpon; //重新开始记录
$dumplimit(); //限制VCD文件的大小(以字节为单位)
$dumpall; //记录所有指定的信号值1234567
usage:
initial
begin
$dumpfile (“verilog. dump”);
$dumpvars (0, testfixture);
end12345
e.g:
$dumpvars; // Dump所有层次的信号
$dumpvars (1, top); // Dump top模块中的所有信号
$dumpvars (2, top. u1); // Dump实例top. u1及其下一层的信号
$dumpvars (0, top. u2, top. u1. u13. q); // Dump top.u2及其以下所有信号,以及信号top. u1. u13. q。
$dumpvars (3, top. u2, top. u1); // Dump top. u1和top. u2及其下两层中的所有信号。
Constraint
- The constraint is written in the.fdc file, and.edif is automatically generated by synplify.
I even don’t konw what the different between .fdc file and .xdc file, seemingly, just sentences has difference, for example those sentence in .xdc file:
set_property PACKAGE_PIN R4 [get_ports "GPIO1"]
set_propert IOSTANDARD "LVCMOS18" [get_ports "GPIO1"]
To .fdc file:
define_attribute {GPIO1} syn_loc {R4}
define_io_standard {p:GPIO1} syn_pad_type {LVCMOS18}
-
-dict is write in one line of constraints associated with a PIN.
e.g:set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { led0_b }];
-
When vivado implementation run place design arise this kind of error:
Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is
acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc
file to demote this message to a WARNING. However, the use of this override is highly
discouraged. These examples can be used directly in the .xdc file to override this clock
rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] >
clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y248
and BUFG_inst (BUFG.I) is locked to BUFGCTRL_X0Y31
Solution:Add this codeset_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
in init.xdc file.
之后开始System Verilog, UVM, Cadence VIP,加油咯。