Vivado [Place 30-574] Poor placement for routing between an IO pin and BUFG 尝试解决

最新推荐文章于 2024-06-28 22:00:52 发布

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最新推荐文章于 2024-06-28 22:00:52 发布

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分类专栏： Verilog 文章标签： Vivado Verilog

本文链接：https://blog.csdn.net/weixin_43162818/article/details/89434960

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场景

Vivado版本： 2016.4
FPGA开发板：NEXYS 4 DDR
所在项目：31条单周期CPU

完整报错信息

[Place 30-574] Poor placement for routing between an IO pin and BUFG. 
		If this sub optimal condition is acceptable for this design, 
		you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file 
		to demote this message to a WARNING. 
		However, the use of this override is highly discouraged. 
		These examples can be used directly in the .xdc file to override this clock rule.
			< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets reset_IBUF] >

		reset_IBUF_inst (IBUF.O) is locked to IOB_X0Y82
		 and reset_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1