VL30 RAM的简单实现

最新推荐文章于 2024-09-10 17:45:18 发布

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最新推荐文章于 2024-09-10 17:45:18 发布

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分类专栏： verilog 文章标签： fpga开发

本文链接：https://blog.csdn.net/ChenGz233/article/details/125174838

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如题
VL29 单端口RAM 与VL30 RAM的简单实现的区别：
单端口RAM只有一个地址输入和一个使能信号
而 RAM的简单实现则将读写分开，拥有两路使能信号和地址信号

rtl代码

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
    reg [3:0] ram[255:0];
    integer i;
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n) begin
         for(i=0;i<256;i=i+1)
                ram[i] <= 0; 
        end
        else begin
            if(write_en)
                ram[write_addr] <= write_data;
            else
                ram[write_addr] <= ram[write_addr];
        end
    end
    
    always@(posedge clk or negedge rst_n) begin
         if(~rst_n)
           read_data <= 0;
        else begin 
            if(read_en)
                read_data <= ram[read_addr];
            else
               read_data <= read_data;
        end
    end
    
endmodule

testbench代码

`timescale 1ns / 1ps

module ram_mod_tb();
    reg clk;
    reg rst_n;
    reg write_en;
    reg [7:0]write_addr;
    reg [3:0]write_data;
    reg read_en;
    reg [7:0]read_addr;
    wire [3:0]read_data;
    
    ram_mod ram_mod_1(
.clk(clk),            
.rst_n(rst_n),          
.write_en(write_en),       
.write_addr(write_addr),
.write_data(write_data),
.read_en(read_en),        
.read_addr(read_addr), 
.read_data(read_data)
    );
    
  real         CYCLE_200MHz = 5 ; //
    always begin
        clk = 0 ; #(CYCLE_200MHz/2) ;
        clk = 1 ; #(CYCLE_200MHz/2) ;
    end
     initial begin
     rst_n = 0;write_en =0;write_addr =0; write_data =0;read_en = 0; read_addr = 0;
     #5 
     rst_n = 1;write_en =1;write_addr =0; write_data =1;read_en = 0; read_addr = 0;
     #5 
     rst_n = 1;write_en =1;write_addr =1; write_data =2;read_en = 0; read_addr = 0;
     #5 
     rst_n = 1;write_en =1;write_addr =2; write_data =4;read_en = 0; read_addr = 0;
     #5 
     rst_n = 1;write_en =0;write_addr =3; write_data =6;read_en = 0; read_addr = 0;
     #5 
     rst_n = 1;write_en =1;write_addr =4; write_data =8;read_en = 0; read_addr = 0;
     #5 
     rst_n = 1;write_en =1;write_addr =5; write_data =10;read_en = 0; read_addr = 0;
     #5 
     rst_n = 1;write_en =0;write_addr =6; write_data =12;read_en = 0; read_addr = 0;
     #5 
     rst_n = 1;write_en =1;write_addr =7; write_data =14;read_en = 0; read_addr = 0;
     #5 
     rst_n = 1;write_en =1;write_addr =7; write_data =14;read_en = 1; read_addr = 0;
     #5 
     rst_n = 1;write_en =1;write_addr =7; write_data =14;read_en = 1; read_addr = 1;
     #5 
     rst_n = 1;write_en =1;write_addr =7; write_data =14;read_en = 1; read_addr = 2;
     #5 
     rst_n = 1;write_en =1;write_addr =7; write_data =14;read_en = 1; read_addr = 3;
     #5 
     rst_n = 1;write_en =1;write_addr =7; write_data =14;read_en = 1; read_addr = 4;
     #5 
     rst_n = 1;write_en =1;write_addr =7; write_data =14;read_en = 1; read_addr = 5;
     #5 
     rst_n = 1;write_en =1;write_addr =7; write_data =14;read_en = 1; read_addr = 6;
     #5 
     rst_n = 1;write_en =1;write_addr =7; write_data =14;read_en = 1; read_addr = 7;

     
     
     
     
     
     end
endmodule