【System Verilog and UVM基础入门4】phase机制

目录

 1. phase机制

1.1 Main UVM Phases

1.2 Phase Definition

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 1. phase机制

All testbench components are derived from uvm_componentand are aware of the phase concept. Each component goes through a pre-defined set of phases, and it cannot proceed to the next phase until all components finish their execution inthe current phase. So UVM phases act as a synchronizing mechanism in the life cycle of a simulation.

Because phases are defined as callbacks, classes derived from uvm_component can perform useful work in the callback phase method. Methods that do not consume simulation time are function s and methods that consume simulation timeare tasks. All phases can be grouped into three categories:

1.Build time phases

2.Run time phases

3.Clean-Up phases