Verilog练习：HDLBits笔记7

三、Circuits

Combinational logic-Basic Gates

1、Wire

Problem Statement：

mplement the following circuit:

module top_module (
    input  in,
    output out
);
    assign out = in;

endmodule

 2、GND

Problem Statement：

Implement the following circuit:

module top_module (
    output out
);
    assign out = 1'b0;

endmodule

 3、NOR

Problem Statement：

Implement the following circuit:

module top_module (
    input  in1,
    input  in2,
    output out
);
    assign out = ~(in1 | in2);

endmodule

 4、Another gate

Problem Statement：

Implement the following circuit:

module top_module (
    input in1,
    input in2,
    output out
);
    assign out = ~in2 & in1;

endmodule

 5、Two gates

Problem Statement：

mplement the following circuit:

module top_module (
    input in1,
    input in2,
    input in3,
    output out
);
    wire out1;
    
    assign out1 = ~(in1 ^ in2);
    assign out = out1 ^ in3;

endmodule

  6、More logic gates

Problem Statement：

Build a combinational circuit with two inputs, a and b.

There are 7 outputs, each with a logic gate driving it:

• out_and: a and b
• out_or: a or b
• out_xor: a xor b
• out_nand: a nand b
• out_nor: a nor b
• out_xnor: a xnor b
• out_anotb: a and-not b

module top_module( 
    input  a, b,
    
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);
    assign out_and   = a & b;
    assign out_or    = a | b;
    assign out_xor   = a ^ b;
    assign out_nand  = ~(a & b);
    assign out_nor   = ~(a | b);
    assign out_xnor  = ~(a ^ b);
    assign out_anotb = a & (~b);    

endmodule

7、7420 chip

Problem Statement：

The 7420 is a chip with two 4-input NAND gates.

Create a module with the same functionality as the 7420 chip. It has 8 inputs and 2 outputs.

module top_module ( 
    input  p1a, p1b, p1c, p1d,
    output p1y,
    
    input  p2a, p2b, p2c, p2d,
    output p2y 
);
    assign p1y = ~(p1a & p1b & p1c & p1d);
    assign p2y = ~(p2a & p2b & p2c & p2d);


endmodule

8、Truth table

Problem Statement：

For a boolean function of N inputs, there are 2N possible input combinations. Each row of the truth table lists one input combination, so there are always 2N rows. The output column shows what the output should be for each input value.

Row	Inputs			Outputs
number	x3	x2	x1	f
0	0	0	0	0
1	0	0	1	0
2	0	1	0	1
3	0	1	1	1
4	1	0	0	0
5	1	0	1	1
6	1	1	0	0
7	1	1	1	1

Create a combinational circuit that implements the above truth table.

 

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    
    output f   // one output
);
    assign f = ((~x3) & x2) | (x3 & x1);

endmodule

9、Two-bit equality

Problem Statement：

Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and produces an output z. The value of z should be 1 if A = B, otherwise z should be 0.

module top_module ( input [1:0] A, input [1:0] B, output z ); 
    
    assign z = (A == B)? 1 : 0;

endmodule

 10、Simple circuit A

Problem Statement：

Module A is supposed to implement the function z = (x^y) & x. Implement this module.

module top_module (input x, input y, output z);
    
    assign z = (x ^ y) & x;

endmodule

11、Simple circuit B

Problem Statement：

Circuit B can be described by the following simulation waveform: 

module top_module ( input x, input y, output z );
    
    assign z = ~(x ^ y);

endmodule

 12、Combine circuits A  and circuits B

Problem Statement：

The top-level design consists of two instantiations each of subcircuits A and B, as shown below.

 Implement this circuit.

module top_module (input x, input y, output z);

    wire z1,z2,z3,z4,z5,z6;
    
    assign z1 = (x ^ y) & x;
    assign z2 = ~(x ^ y);
    assign z3 = (x ^ y) & x;
    assign z4 = ~(x ^ y);
    
    assign z5 = z1 | z2;
    assign z6 = z3 & z4;
    
    assign z  = z5 ^ z6;
    
endmodule

13、Ring or vibrate

Problem Statement：

Suppose you are designing a circuit to control a cellphone's ringer and vibration motor. Whenever the phone needs to ring from an incoming call (input ring), your circuit must either turn on the ringer (output ringer = 1) or the motor (output motor = 1), but not both. If the phone is in vibrate mode (input vibrate_mode = 1), turn on the motor. Otherwise, turn on the ringer.

Try to use only assign statements, to see whether you can translate a problem description into a collection of logic gates.

module top_module (
    input  ring,
    input  vibrate_mode,
    output ringer,      
    output motor        
);
    assign ringer = ring & (~vibrate_mode);
    assign motor  = ring & vibrate_mode;

endmodule

14、Thermostat 

Problem Statement：

A heating/cooling thermostat controls both a heater (during winter) and an air conditioner (during summer). Implement a circuit that will turn on and off the heater, air conditioning, and blower fan as appropriate.

The thermostat can be in one of two modes: heating (mode = 1) and cooling (mode = 0). In heating mode, turn the heater on when it is too cold (too_cold = 1) but do not use the air conditioner. In cooling mode, turn the air conditioner on when it is too hot (too_hot = 1), but do not turn on the heater. When the heater or air conditioner are on, also turn on the fan to circulate the air. In addition, the user can also request the fan to turn on (fan_on = 1), even if the heater and air conditioner are off.

Try to use only assign statements, to see whether you can translate a problem description into a collection of logic gates.

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    
    output heater,
    output aircon,
    output fan
); 
    
	assign heater = mode & too_cold;
	assign aircon = ~mode & too_hot;
	assign fan    = heater | aircon | fan_on;
    
endmodule

 15、3-bit population count

Problem Statement：

A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 3-bit input vector.

module top_module( 
    input  [2:0] in,
    output [1:0] out );
    
    assign out = in[2] + in[1] + in[0];

endmodule

 16、Gates and vectors

Problem Statement：

You are given a four-bit input vector in[3:0]. We want to know some relationships between each bit and its neighbour:

• out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left (higher index) are '1'. For example, out_both[2] should indicate if in[2] and in[3] are both 1. Since in[3] has no neighbour to the left, the answer is obvious so we don't need to know out_both[3].
• out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are '1'. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don't need to know out_any[0].
• out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[2] should indicate if in[2] is different from in[3]. For this part, treat the vector as wrapping around, so in[3]'s neighbour to the left is in[0].

module top_module( 
    input [3:0] in,
    
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );
    
    assign out_both[2:0] = in[2:0] & in[3:1];
    assign out_any[3:1] = in[3:1] | in[2:0];
    assign out_different[3:0] = in[3:0] ^ {in[0],in[3:1]};

endmodule

17、Even longer vectors

Problem Statement：

You are given a 100-bit input vector in[99:0]. We want to know some relationships between each bit and its neighbour:

• out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left are '1'. For example, out_both[98] should indicate if in[98] and in[99] are both 1. Since in[99] has no neighbour to the left, the answer is obvious so we don't need to know out_both[99].
• out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are '1'. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don't need to know out_any[0].
• out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[98] should indicate if in[98] is different from in[99]. For this part, treat the vector as wrapping around, so in[99]'s neighbour to the left is in[0].

module top_module( 
    input [99:0] in,
    
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );
    
    assign out_both[98:0] = in[98:0] & in[99:1];
    assign out_any[99:1] = in[99:1] | in[98:0];
    assign out_different[99:0] = in[99:0] ^ {in[0],in[99:1]};

endmodule