[Opt 31-66] Net ila0/inst/ila_core_inst/TRIGGER_I[82] is driverless and is driving the D pin of shif

【代码】

wire clock_locked;
wire clock50;
clk_wiz_0 clk_wiz_0(
    .clk_in1(clock), // 输入10MHz时钟
    .clk_out1(clock50), // 输出50MHz时钟
    .reset(!nrst),
    .locked(clock_locked)
);

ila_0 ila0(
    .clk(clock50), // ILA使用的是倍频后的50MHz时钟
    .probe0(i), // [3:0]
    .probe1(state), // [3:0]
    .probe2(ad5660_spi_request),
    .probe3(ad5660_spi_ready),
    .probe4(ad5660_spi_bits_cnt), // [15:0]
    .probe5(uart_rx),
    .probe6(uart_bytearray_rx_request),
    .probe7(uart_bytearray_rx_complete),
    .probe8(uart_bytearray_rx_error),
    .probe9(uart_bytearray_receiver.wait_first),
    .probe10(uart_bytearray_receiver.remaining_time), // [31:0]
    .probe11(uart_bytearray_rx_size), // [7:0]
    .probe12(uart_bytearray_rx_remaining), // [7:0]
    .probe13(uart_tx),
    .probe14(ad5660_spi_sync),
    .probe15(ad5660_spi_sclk),
    .probe16(ad5660_spi_din)
);

【错误提示】

[Opt 31-66] Net ila0/inst/ila_core_inst/TRIGGER_I[82] is driverless and is driving the D pin of shifted_data_in_reg[7][82]_srl8. If the entire cell is not removed or a driver added to the net, this will trigger an error after the design has been optimized.

【解决方案】

第82个信号（从0开始数）刚好是ad5660_spi_din这一信号，给这个信号加一级wire即可解决问题。

wire _ad5660_spi_din = ad5660_spi_din;
ila_0 ila0(
    .clk(clock50),
    .probe0(i), // [3:0]
    .probe1(state), // [3:0]
    .probe2(ad5660_spi_request),
    .probe3(ad5660_spi_ready),
    .probe4(ad5660_spi_bits_cnt), // [15:0]
    .probe5(uart_rx),
    .probe6(uart_bytearray_rx_request),
    .probe7(uart_bytearray_rx_complete),
    .probe8(uart_bytearray_rx_error),
    .probe9(uart_bytearray_receiver.wait_first),
    .probe10(uart_bytearray_receiver.remaining_time), // [31:0]
    .probe11(uart_bytearray_rx_size), // [7:0]
    .probe12(uart_bytearray_rx_remaining), // [7:0]
    .probe13(uart_tx),
    .probe14(ad5660_spi_sync),
    .probe15(ad5660_spi_sclk),
    .probe16(_ad5660_spi_din)
);