[Opt 31-67] Problem axi_interconnect RTL报错

最新推荐文章于 2024-08-14 11:55:54 发布

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最新推荐文章于 2024-08-14 11:55:54 发布

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分类专栏： FPGA 文章标签： [Opt 31-67] Problem

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[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: pl_ddr_axi_interconnect_u/inst/axi_interconnect_inst/crossbar_samd/gen_samd.crossbar_samd/gen_crossbar.gen_slave_slots[1].gen_si_write.splitter_aw_si/FSM_onehot_state[2]_i_2__0.

在添加IP综合选项时，选择Global即可解决问题。添加IP核时选择OOC（Out of context ip）会导致上述综合问题。