习题笔记 Exams/ece241 2013 q4

最新推荐文章于 2024-09-12 17:09:49 发布

Zephyr_R

最新推荐文章于 2024-09-12 17:09:49 发布

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分类专栏： Verilog 文章标签： fpga开发 Powered by 金山文档

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文章介绍了两种使用Verilog设计的状态机方法，用于处理水位传感器的信号。方法一是建立一个六状态的状态机，结合了水位上升和下降的状态，同时包含了同步复位功能，使状态机在复位后回到长期低水位的输出状态。方法二是分开处理FR和DFR的状态，根据当前状态和前一状态来决定输出。

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Also include an active-high synchronous reset that resets the state machine to a state equivalent to if the water level had been low for a long time (no sensors asserted, and all four outputs asserted).

方法一：采用六个状态的fsm

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output reg fr3,
    output reg fr2,
    output reg fr1,
    output reg dfr
);
 //将水位传感器与前后升落状态合在一起共6个状态
    parameter s0=0, rise_to_s1=1, fall_to_s1=2, rise_to_s2=3, fall_to_s2=4, s3=5;
    reg [2:0] state, next;        
    

    always @(posedge clk) 
    begin
          if (reset) 
        state <= s0;
          else 
        state <= next;
      end
   
    always@(*)
    begin
          case (state)
              s0:         next = s[1] ? rise_to_s1 : s0;
              rise_to_s1: next = s[2] ? rise_to_s2 : (s[1] ? rise_to_s1 : s0);
              fall_to_s1: next = s[2] ? rise_to_s2 : (s[1] ? fall_to_s1 : s0);
              rise_to_s2: next = s[3] ? s3 : (s[2] ? rise_to_s2 : fall_to_s1);
              fall_to_s2: next = s[3] ? s3 : (s[2] ? fall_to_s2 : fall_to_s1);
              s3:         next = s[3] ? s3 : fall_to_s2;
              default:    next = 'x;
          endcase
    end
    
    always@(*) 
    begin
          case (state)
              s0:         {fr3, fr2, fr1, dfr} = 4'b1111;
              rise_to_s1: {fr3, fr2, fr1, dfr} = 4'b0110;
              fall_to_s1: {fr3, fr2, fr1, dfr} = 4'b0111;
              rise_to_s2: {fr3, fr2, fr1, dfr} = 4'b0010;
              fall_to_s2: {fr3, fr2, fr1, dfr} = 4'b0011;
              s3:         {fr3, fr2, fr1, dfr} = 4'b0000;
              default:    {fr3, fr2, fr1, dfr} = 'x;
          endcase
      end
    
endmodule

方法二：分别讨论fr与dfr状态

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 
    reg [3:0]state,pre_state;

    parameter s0=3'b000, s1=3'b001, s2=3'b011,s3=3'b111;
    //由当前state与pre_state控制dfr
    always @(*)
      case(state)
      s0:dfr = 1'b1;
      s1:dfr = (pre_state==s2 ? 1'b1:1'b0);
      s2:dfr = (pre_state==s3 ? 1'b1:1'b0);
      s3:dfr = 1'b0;
      endcase

    //由state控制fr
    always @(*)
      case(state)
      s0: {fr3,fr2,fr1}=3'b111;
      s1: {fr3,fr2,fr1}=3'b011;
      s2: {fr3,fr2,fr1}=3'b001;
      s3: {fr3,fr2,fr1}=3'b000;
      endcase
    
    
    always @(posedge clk)
      if (reset)
        begin 
          state <= s0;
          pre_state <= s1;
        end
      else if (s!=state)     //当传感器与当前state不一致时，更新state与pre_state
           begin
            pre_state <= state;
            state <= s;
           end

endmodule