1.Quartus中:Warning (21074)
Warning (21074): Design contains 10 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "pix_y[0]"
...
警告:设计中的10个输入引脚信号没有驱动逻辑
原因:输入信号pix_y没有被调用,若确实没有使用可忽略此报错信息。
常见错误场景:复制粘贴类似代码时,一些变量名称没改。
2.ModelSim中:
Error: F:/FPGA/MyCode/rs232/quartus_prj/../sim/tb_rs232.v(34): 'j' is an invalid type in Generate loop. Must be a genvar.
Error: (vlog-13069) F:/FPGA/MyCode/rs232/quartus_prj/../sim/tb_rs232.v(36): near "endtask": syntax error, unexpected endtask.
Error: F:/FPGA/MyCode/rs232/quartus_prj/../sim/tb_rs232.v(45): 'i' is an invalid type in Generate loop. Must be a genvar.
Error: (vlog-13069) F:/FPGA/MyCode/rs232/quartus_prj/../sim/tb_rs232.v(48): near "<=": syntax error, unexpected <=.
Error: F:/FPGA/MyCode/rs232/quartus_prj/../sim/tb_rs232.v(48): (vlog-13205) Syntax error found in the scope following 'rx'. Is there a missing '::'?
错误原因:tb_rs232.v(32)处的关键字task拼错。
3.Quartus中:Warning (21074)
Warning (21074): Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "rx"
警告:设计中的1个输入引脚信号没有驱动逻辑
原因:输入信号rx没有被调用,若确实没有使用可忽略此报错信息。
常见错误场景:
a.复制粘贴类似代码时,一些变量名称没改。
b.代码逻辑错误,导致编译器自动将该信号优化掉了。
3.Quartus中:Warning (10240)
Warning (10240): Verilog HDL Always Construct warning at data_reg_deal.v(98) inferring latch(es) for variable "reg_f_32", which holds its previous value in one or more paths through the always construct
case语句有问题,比如:
1 case(pi_cnt)
2 4'd2: reg_f_32[7:0] <= pi_data[7:0];
3 4'd3: reg_f_32[15:8] <= pi_data[7:0];
4 4'd4: reg_f_32[23:16] <= pi_data[7:0];
5 4'd5: reg_f_32[23:16] <= pi_data[7:0];
6 default:reg_f_32 <= reg_f_32;
7 endcase
其中,第4,5行执行语句相同,quartus就会警告。若非故意写错,可忽略。
我这里写错了,第5行应该为:
5 4'd5: reg_f_32[31:24] <= pi_data[7:0];
修改后,警告消失。