https://hdlbits.01xz.net/wiki/Exams/review2015_fsm
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output shift_ena,
output counting,
input done_counting,
output done,
input ack );
parameter S0=0,S1=1,S2=2,S3=3,S4=4,S5=5,S6=6,S7=7,S8=8,S9=9;
reg [4:0] cs,ns;
always @(*)
begin
case (cs)
S0:ns=data?S1:S0;
S1:ns=data?S2:S0;
S2:ns=data?S2:S3;
S3:ns=data?S4:S0;
S4:ns=S5;// S4 ~ S7 shift_ena = 1
S5:ns=S6;
S6:ns=S7;
S7:ns=S8; // S8 counting =1
S8:ns=done_counting?S9:S8; //S9 ,done = 1
S9:ns=ack?S0:S9;
endcase
end
always @(posedge clk)
begin
if (reset)
cs<= S0;
else
cs<= ns;
end
assign shift_ena = (cs==S4)|(cs==S5)|(cs==S6)|(cs==S7);
assign counting = (cs==S8);
assign done = (cs==S9);
endmodule