偶数倍分频器

要求：实现一个8分频器，要求占空比为50%

零、分析
可以用计数器来控制输出的翻转。计数器从0技术到7，输出信号分别在3,7进行翻转。由此得到50%占空比，周期为8T的分频器。

一、Verilog代码

module Frequency_divider8 (
    input clk,
    input rst_n,
    output reg div8
);
    reg [2:0] count;

    always @(posedge clk) begin
        if (!rst_n)
            count <= 3'd0;
        else if(count == 3'd7)
            count <= 3'd0;
        else
            count <= count + 1;
    end

    always @(posedge clk) begin
        if (!rst_n)
            div8 <= 1'b1;
        else if(count == 3'd3 | count == 3'd7)
            div8 <= !div8;
        else
            div8 <= div8;
    end

endmodule

二、test bench

`timescale 1ns/1ps
module Frecuency_divider8_tb; 

parameter clock_cycle = 20;
reg clk;
reg rst_n;
wire div8;

initial begin
    clk = 0;
    rst_n = 1;

    #clock_cycle rst_n = 0;
    #clock_cycle rst_n = 1;
end

always #(clock_cycle/2) clk = ~clk;

Frequency_divider8 div8_half_duty(
    .clk    (clk),
    .rst_n  (rst_n),
    .div8   (div8)
);

endmodule