#FPGA（全加器设计）

1.IDE:Quartus II

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2.设备：Cyclone II  EP2C8Q208C8N  

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3.实验：全加器设计

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4.时序图：

in1	in2	cin	sum	count
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

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5.步骤

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6.代码：

全加器代码

/*
 *全加器
 *   in1         in2          cin      sum         count
 *   0           0            0         0          0      
 *   0           0            1         1          0
 *   0           1            0         1          0
 *   0           1            1         0          1
 *   1           0            0         1          0
 *   1           0            1         0          1
 *   1           1            0         0          1
 *   1           1            1         1          1
 *
 */
module full_adder(
input    wire     in1,
input    wire     in2,
input    wire     cin,

output   wire     count,
output   wire     sum
);


wire     sum0;
wire     count0;
wire     count1;
  
/*
 *实例化两个半加器
 */
half_adder half_adder_inst0(
 .in1     (in1)      ,
 .in2     (in2)      ,

 .sum     (sum0)     ,
 .count   (count0)
);


half_adder half_adder_inst1(
 .in1     (sum0)     ,
 .in2     (cin)      ,

 .sum     (sum)      ,
 .count   (count1)
);

/*
 *全加器进位
 */
assign  count = (count0 | count1);

endmodule

 全加器仿真代码

/*
 *全加器仿真代码
 */
`timescale 1ns/1ns

module tb_full_adder();

reg                in1;
reg                in2;
reg                cin;

wire               sum;
wire             count;

/*
 *初始化
 */
initial
    begin
	     in1  <=  1'b0;
		  in2  <=  1'b0;
		  cin  <=  1'b0;
	 end

/*
 *监视窗
 */
initial
    begin
	     $timeformat(-9,0,"ns",6);    //ns 无小数位  6位位宽
	     $monitor("@time %t:in1=%b,in2=%b,cin=%b,sum=%b,count=%b",$time,in1,in2,cin,sum,count);
	 end

/*
 *随机赋值
 */
always #10 in1 <= {$random} % 2 ; 
always #10 in2 <= {$random} % 2 ; 
always #10 cin <= {$random} % 2 ; 

/*
 *实例化
 */
 full_adder full_adder_inst
 (
          . in1    (in1)   ,
          . in2    (in2)   ,
          . cin    (cin)   ,
          
          . count  (count) ,
          . sum    (sum)
 );
 
 endmodule
 

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