FPGA时钟之gated-clk设计

Gated Clock

ASIC designs typically gate clocks to conserve power, with custom clock trees defined for each individual tree. 

The solution is to separate the gating from the clock inputs, and combine individual clocks trees on the dedicated FPGA global clock trees. The software logically separates the gating from the clock and routes the gating to the

clock enables on the sequential devices, using the programmable routing resources of the FPGA.

使用synplify的Specifying Design-Level Optimizations选项fixed gated clock会将clk端的gated逻辑综合至D触发器的CE端，减少clk tree的延时，避免导致不必要的timing问题。