【电路图转Verilog】
【一】
代码
module mul_module(
mul_a ,
mul_b ,
clk ,
rst_n ,
mul_result
);
parameter A_W = 4;
parameter B_W = 3;
parameter C_W = A_W + B_W;
input[A_W-1:0] mul_a;
input[B_W-1:0] mul_b;
input clk ;
input rst_n;
output[C_W-1:0] mul_result;
reg [C_W-1:0] mul_result;
reg [C_W-1:0] mul_result_tmp;
always @(*)begin
mul_result_tmp=mul_a * mul_b;
end
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
mul_result <= 0;
end
else begin
mul_result <= mul_result_tmp;
end
end
endmodule
RTL电路图
【二】
代码
module mul2port(
din_a,
din_b,
din_c,
din_d,
sel_a,
sel_b,
clk ,
rst_n,
result_a,
result_b
);
input[3-1:0] din_a;
input[2-1:0] din_b;
input[4-1:0] din_c;
input[4-1:0] din_d;
input sel_a;
input sel_b;
input clk ;
input rst_n;
output[7-1:0] result_a;
output[6-1:0] result_b;
reg [7-1:0] result_a;
reg [6-1:0] result_b;
reg [4-1:0] sel_dout;
wire [7-1:0] result_a_tmp;
wire [6-1:0] result_b_tmp;
reg sel;
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
result_b <= 0;
end
else begin
result_b <= result_b_tmp;
end
end
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
result_a <= 0;
end
else begin
result_a <= result_a_tmp;
end
end
mul_module#(.A_W(3),.B_W(4)) mul_4_3(
.mul_a (din_a),
.mul_b (sel_dout),
.clk (clk),
.rst_n (rst_n),
.mul_result(result_a_tmp)
);
mul_module#(.A_W(2),.B_W(4)) mul_4_2(
.mul_a (din_b),
.mul_b (sel_dout),
.clk (clk),
.rst_n (rst_n),
.mul_result(result_b_tmp)
);
always @(*)begin
if(sel==0)begin
sel_dout = din_c;
end
else begin
sel_dout = din_d;
end
end
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
sel <= 1'b0;
end
else begin
sel <= sel_a & sel_b;
end
end
endmodule
RTL电路图
【三】
代码
module testtt(
clk ,
rst_n ,
enable,
datain,
F ,
);
input enable;
input datain;
input rst_n ;
input clk ;
output F;
reg F ;
reg result_D1 ;
reg result_D2 ;
reg result_D2_tmp;
reg result_D3 ;
always @(*)begin
F = result_D1 && result_D2_tmp && result_D3 ;
end
always @(*)begin
result_D2_tmp = ~ result_D2;
end
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
result_D3 <= 0;
end
else begin
result_D3 <= result_D2;
end
end
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
result_D2 <= 0;
end
else begin
result_D2 <= result_D1;
end
end
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
result_D1 <= 0;
end
else begin
result_D1 <= enable && datain;
end
end
endmodule
RTL电路图
【四】
代码
module note(
clk ,
rst_n ,
out
);
parameter DATA_W = 4;
input clk ;
input rst_n ;
output[DATA_W-1:0] out;
reg [DATA_W-1:0] out;
reg out_temp;
always@(*)begin
out_temp = out + 1'b1;
end
always@(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)begin
out <= 0;
end
else begin
out <= out_temp;
end
end
endmodule
RTL电路图
【测试练习】
【1】
功能:datain的“101”序列检查,如果datain先后为“101”,则F输出高电平,否则F为低电平。
编写测试文件,进行仿真,输出波形如下(其中rst时间不做要求):
代码
`timescale 1 ns/1 ns
module testbench_name();
reg clk ;
reg rst_n;
reg enable ;
reg datain ;
wire F;
parameter CYCLE = 20;
parameter RST_TIME = 3 ;
datain uut(
.clk (clk ),
.rst_n (rst_n ),
.enable (enable ),
.datain (datain ),
.F (F )
);
//生成本地時鐘50M
initial begin
clk = 0;
forever
#(CYCLE/2)
clk=~clk;
end
//產生復位信號
initial begin
rst_n = 1;
#2;
rst_n = 0;
#(CYCLE*RST_TIME);
rst_n = 1;
end
//輸入信號din0賦值方式
initial begin
#1;
enable = 0 ;
#(CYCLE*(RST_TIME+1));
enable = 0 ;
#(CYCLE*9);
enable = 1 ;
end
//輸入信號din1賦值方式
initial begin
#1;
datain = 0 ;
#(CYCLE*(RST_TIME+1));
datain = 1 ;
#(CYCLE*1);
datain = 0 ;
#(CYCLE*1);
datain = 1 ;
#(CYCLE*1);
datain = 0 ;
#(CYCLE*2);
datain = 1 ;
#(CYCLE*2);
datain = 0 ;
#(CYCLE*1);
datain = 1 ;
#(CYCLE*1);
datain = 0 ;
#(CYCLE*1);
datain = 1 ;
#(CYCLE*1);
datain = 0 ;
#(CYCLE*1);
datain = 1 ;
#(CYCLE*1);
datain = 0 ;
end
endmodule