文章目录
本篇博客介绍TMAXug系列的 ATPG Design Flow
ATPG process是一个产生测试向量的过程,让ATE设备能够识别到正确的电路与fault 电路。
产生tmax,要产生ATPG需要三个文件:Netlist、Library Models、STIL procedures(SPF)
如何启动tmax运行脚本
tmax -shell spec_command_file.cmd
基本的脚本如下:
set_messages log last_run.log -replace
# read design and libraries
read_netlist spec_design.v -delete
read_netlist /home/vendor/verilog/*.v -noabort
report_modules -summary
report_modules -error
#build design model
run_build_model spec_top_level_name
report_rules -fail
# define clocks and pin constraints
add_clocks 1 CLK MCLK SCLK
add_clocks 0 resetn iosc14m
add_pi_constraints 1 testmode
#define scan chains & STIL procedures,perform DRC checks
run_drc spec_design.spf
report_rules -fail
report_nonscan_cells -summary
report_buses -summary
report_feedback_paths -summary
#create patterns
set_atpg -aboart 20 -pat 1500 -merge high
add_faults -all
run_atpg -auto_compresson
report_summaries
#---
report_faults -level 5 64 -class au -collapse -verbose
write_faults faults.all -all -replace
write_patterns.v -formate verilog -parallel 2 -replace
exit