SRAM FPGA控制，实际产品拷机测试过

最新推荐文章于 2024-08-01 07:34:08 发布

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最新推荐文章于 2024-08-01 07:34:08 发布

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分类专栏： FPGA/ZYNQ/MPSOC

本文链接：https://blog.csdn.net/feihu612/article/details/108140254

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	源码来自： https://bbs.21ic.com/icview-3013844-1-1.html

`timescale 1ns / 1ps
	module SRAM_CTRL(
	output reg fifo_in_rdreq,
	input fifo_in_rdfull,
	input [15:0] fifo_in_data,
	input [5:0]  fifo_in_rdusedw,
	
	input FCLK_50M,
	input rst_n,
	output [17:0] SRAM_ADR,
	inout [15:0] SRAM_DAT,
	output SRAM_CSL,
	output SRAM_WEL,
	output SRAM_OEL,
	output SRAM_DQMH,
	output SRAM_DQML,
	
	output reg				fifo_out_wrreq,
	output reg [15:0] 	fifo_out_data
	);
	//
	parameter IDLE = 3'b001;
	parameter S_WR = 3'b010;
	parameter S_RD = 3'b100;

	
	//SRAM TEST
	assign SRAM_DQMH = 1'b0;
	assign SRAM_DQML = 1'b0;
	assign SRAM_CSL = 1'b0;

	
	//------------------------------------------------------------------
	reg [2:0] s_sate;
	reg [5:0] fifo_out_cnt;
	always @ (posedge FCLK_50M)
	begin
		if(!rst_n) s_sate <= IDLE;
		else
			case(s_sate)
			IDLE: if(fifo_in_rdfull) s_sate <= S_WR;
			S_WR: if(fifo_in_rdusedw == 6'd1) s_sate <= S_RD;
			S_RD: if(&fifo_out_cnt) s_sate <= IDLE;
			endcase
	end
	//------------------------------------------------------------------