[SV]SystemVerilog Constraints(1)

                            SystemVerilog Constraints(1)

 

一、Soft Constraints

       SystemVerilog constraints declared with the keyword soft is called as soft constraints. any conflict between class constraint and inline constraint leads to a randomization failure, from this it is clear that it is not possible to override the class constraint by inline constraint. Some test scenarios demand to override the constraints, this can be done by writing a soft keyword in class constraint.

       A soft constraint is a constraint on a random variable, which allows overriding the constraint.

constraint c_name { 
  soft variable { condition }; 
}

       （1）real-time use of soft constraint

This is one of the situations where soft constraints are useful.
Lets Consider, In a verification testbench transaction class constraint is written to generate normal stimulus. For error stimulus generation, error testcase need to have an inline constraint that may conflict with the constraint defined inside the class. In this situation, we have only the option to change the constraint defined inside the transaction class, but changing the constraint in the transaction class will reflect in all other test cases. so this kind of problem can be avoided using soft constraints.

       （2）soft constraint examples --> Conflict between constraints

       In the example below,In the class packet, the addr variable is constrained to greater than 6 and the same addr variable is constrained to less than 6 in the inline constraint. that means expecting the value of addr to be less than and greater than 6, this is not possible and leads to a randomization failure. this problem is resolved in the next example using soft constraint.

class packet;
  rand bit [3:0] addr;
  constraint addr_range { addr > 6; }
endclass
 
module soft_constr;
  initial begin
    packet pkt;
    pkt = new();
 
    repeat(2) begin
      pkt.randomize() with { addr < 6;};
      $display("\taddr = %0d",pkt.addr);
    end
  end
endmodule

• Simulator Output 

Constraints inconsistency failure Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewritethem.
addr = 0

       （3）Using soft constraint

       In the example below,a previous example problem is solved using soft constraints,Constraint declared inside the class will get suppressed by inline constraints.

class packet;
  rand bit [3:0] addr;
  constraint addr_range { soft addr > 6; }
endclass
 
module soft_constr;
  initial begin
    packet pkt;
    pkt = new();
 
    repeat(2) begin
      pkt.randomize() with { addr < 6;};
      $display("\taddr = %0d",pkt.addr);
    end
  end
endmodule

• Simulator Output 

addr = 1
addr = 3

 

二、Unique Constraint

       SystemVerilog constraint defined with the keyword unique is called as a unique constraint. On randomization, unique values to set of variables or unique elements to an array can be generated by using unique constraints.

    Unique constraint allows us to,

• Generate unique values across the variables
• Generate unique elements in an array (Fixed Size Array, Dynamic Array, Associative array and Queue)

constraint c_name { 
  unique {variable's/array}; 
}

    Below example shows,

• Generation of random unique values to the variables var_1, var_2 and var_3
• Generation of random unique elements to an array array

       （1）Unique constraint example --> Unique elements

       In the below example,On randomization unique values to a variable var_1, var_2, var_3 can be obtained by writing unique constraints. Also, a unique constraint is written to an array to get unique array elements.

class unique_elements;
  rand bit [3:0] var_1,var_2,var_3;
  rand bit [7:0] array[6];
  constraint varis_c {unique {var_1,var_2,var_3};}
  constraint array_c {unique {array};}
   
  function void display();
    $display("var_1 = %p",var_1);
    $display("var_2 = %p",var_2);
    $display("var_3 = %p",var_3);
    $display("array = %p",array);
  endfunction
endclass
 
program unique_elements_randomization;
  unique_elements pkt;
 
  initial begin
    pkt = new();
    pkt.randomize();
    pkt.display();  
  end

• Simulator Output 

var_1 =  8

var_2 = 14

var_3 = 11

array = ‘{‘h81, ‘h7b, ‘h4, ‘h47, ‘he1, ‘h17}

       （2）unique array of elements example

       In below example,Unique elements for an array is generated by using a unique keyword. Also considered that the value of elements is less than 10.

class unique_elements;
  rand bit [31:0] array[10];
   
  constraint array_c {unique {array};
                      foreach(array[i]) array[i] < 10;}
   
  function void display();
    $display("array = %p",array);
  endfunction
endclass
 
program unique_elements_randomization;
  unique_elements pkt;
 
  initial begin
    pkt = new();
    pkt.randomize();
    pkt.display();  
  end
   
endprogram

• Simulator Output 

array = ‘{‘h5, ‘h7, ‘h8, ‘h1, ‘h6, ‘h9, ‘h2, ‘h3, ‘h4, ‘h0}

 

三、Bidirectional Constraints

       SystemVerilog constraints are solved bidirectionally, which means constraints on all random variables will be solved parallel.Consider a constraint example,

constraint c_name { if(a == 0) b == 1;
                    else       b == 0; 
}

       We see that ‘b’ is dependent on ‘a’.but constraint solver see’s it as ‘a’ is dependent on ‘b’ and ‘b’ is dependent on ‘a’.
i.e if ‘b’ is inline constrained as ‘1’, in order to satisfy, ‘a’ should take the value ‘0’.

       As constraints are considered from all the aspects, SystemVerilog constraints are called as bidirectional constraints.

       （1）Bidirectional constraint example

       In the example below,Value of a should be sum of b and c, b should be greater than 6 and c should be less than 8. so in this case constraint solver will choose a value to ‘a’ in such a way that it should be sum of b and c, also ‘b’ and ‘c’ should satisfies their constraint.

class packet;
  rand bit [3:0] a;
  rand bit [3:0] b;
  rand bit [3:0] c;
 
  constraint a_value { a == b + c; }
  constraint b_value { b > 6; }
  constraint c_value { c < 8; }
endclass
 
module bidirectional_constr;
  initial begin
    packet pkt;
    pkt = new();
    repeat(5) begin
      pkt.randomize();
      $display("Value of a = %0d \tb = %0d \tc =%0d",pkt.a,pkt.b,pkt.c);
    end
  end
endmodule

• Simulator Output  

Value of a = 8 b = 8 c =0
Value of a = 0 b = 14 c =2
Value of a = 14 b = 14 c =0
Value of a = 6 b = 15 c =7
Value of a = 13 b = 11 c =2

 

       In below example,Generation of value for b is depending on value of a. i.e if(a == 0)  b = 1;this condition can be re-written as,if(b == 1)  a = 0;but there is a constraint for ‘a’ that value for ‘a’ should be always ‘1’. so ‘b’ should not take value of ‘1’ (to satisfy constraint if(a == 0) b == 1;) What if we make ‘b’ value as ‘1’ with inline constraint? See the below example for the answer.

class packet;
  rand bit a;
  rand bit b;
 
  constraint a_value { a == 1; }
  constraint b_value { if(a == 0) b == 1;
                       else       b == 0; }
endclass
 
module bidirectional_const;
  initial begin
    packet pkt;
    pkt = new();
    pkt.randomize() with { b == 1; };
    $display("Value of a = %0d \tb = %0d",pkt.a,pkt.b);
  end
endmodule

• Simulator Output  

Error-[CNST-CIF] Constraints inconsistency failure testbench.sv, 18
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite them.