verilog 关于read握手打拍

针对1bit信号进行打拍，直接使用寄存器打拍；针对带ready握手的信号打拍，我们通常采用同步FIFO处理，故针对ready握手打1拍其实就是使用FIFO为1的逻辑实现，为了优化资源，我们可以删除FIFO中的指针处理，寄存器存储以及寄存器等资源，优化打拍资源。

verilog 代码

module ready_handshake(
  input  wire  				clk,
  input  wire 				rst_n,
  
  input  wire 				push_valid,
  input  wire [WIDTH -1:0] 	push_data,
  output wire 				push_ready,
  
  output reg				pop_valid,
  output reg  [WIDTH -1:0] 	pop_data,
  input  wire 				pop_ready
);

reg 					write_en;	//write enable
reg 					read_en;	//read enable

assign push_ready 	= ~push_full; 
assign write_en 	= push_valid & push_ready;

assign pop_valid    = push_full;
assign read_en      = pop_valid & pop_ready;

always @(posedge clk or negedge rst_n) begin
  if(~rst_n)
	pop_data <= 'd0;
  else if(write_en)
	pop_data <= push_data;
end
always @(posedge clk or negedge rst_n) begin
  if(~rst_n) 
	push_full <= 1'b0;
  else if(write_en)
	push_full <= 1'b1; 
  else if(read_en)
    push_full <= 1'b0;
end

endmodule

由代码可知，由于该逻辑深度为1，故写入数据即满，读出数据即空.