verilog for循环中force的用法

sunvally

已于 2022-11-10 17:26:03 修改

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分类专栏：数字验证文章标签： verilog force loop

于 2022-06-07 10:21:34 首次发布

本文链接：https://blog.csdn.net/hungtaowu/article/details/125160400

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Force and release inside for loop with hierarchical paths

参考文章：https://verificationacademy.com/forums/systemverilog/force-and-release-inside-loop-hierarchical-paths

for (genvar i=0;i<channel;i++) begin 
initial
  begin
   force a.b.c.g[i].d.e.rst_n=0;
   #10ns;
   release a.b.c.g[i].d.e.rst_n;
  end
end

Force with delay

reg [env_common_dec::CH_NUM-1:0] tx_en_delay_p;
reg [env_common_dec::CH_NUM-1:0] tx_en_delay_n;

for (genvar i = 0; i < env_common_dec::CH_NUM; i++) begin
    always @(*) tx_en_delay_p[i] <= #env_common_dec::TX_EN_DELAY  `U_MODULE1_TOP.o_tx_en[i];
    always @(*) tx_en_delay_n[i] <= #env_common_dec::TX_EN_DELAY ~`U_MODULE1_TOP.o_tx_en[i];

    initial begin
        parameter TH_NUM = env_common_dec::TH_NUM;

        force `U_MODULE2_TOP.i_in_p[(i*(TH_NUM+1)+0)+:1] = tx_en_delay_p;
        force `U_MODULE2_TOP.i_in_n[(i*(TH_NUM+1)+0)+:1] = tx_en_delay_n;
    end
end