使用工:Xilinx ISE 14.7
在这里涉及到了Verilog的条件语句对真值表进行翻译,因为有8种情况,所以选择case语句,代码如下:
module code(
input [2:0] in,
output reg [7:0] led
);
always @ (*)
case(in)
3'b000: led = 8'b00000001;
3'b001: led = 8'b00000010;
3'b010: led = 8'b00000100;
3'b011: led = 8'b00001000;
3'b100: led = 8'b00010000;
3'b101: led = 8'b00100000;
3'b110: led = 8'b01000000;
3'b111: led = 8'b10000000;
endcase
endmodule
注意:由于使用always控制时序触发,在always里要使用reg而不是使用前文中的wire,wire适用与组合逻辑,用assign赋值
小建议:这是刚学时所写的程序,语法不规范,最好在always下加个begin——end把case的内容囊括起来
测试文件:
initial begin
// Initialize Inputs
in = 0;
#100;
in = 1;
#100;
in = 2;
#100;
in = 3;
#100;
in = 4;
#100;
in = 5;
#100;
in = 6;
#100;
in = 7;
#100;
//end
// Wait 100 ns for global reset to finish
// Add stimulus here
end
仿真结果: