输出周期波形信号（verilog语言）

刚开始接触硬件设计，用各种循环语句写了 周期波形信号电路
Always
module xhalways;
reg clock;
//Initialize clock at time zero
initial
        clock = 1'b0;
//Toggle clock every half cycle (time period = 20)
always
        #30 clock = ~clock;
always
        #10 clock = ~clock;
     
endmodule
 
 
forever
module clock_gen;
//Example 1: Clock generation
//Use forever loop instead of always block
reg clock;
 
initial
begin
        clock = 1'b0;
        forever #10 clock = ~clock; //Clock with period of 20 units
        forever #10 clock = ~clock;
end
 
//initial
       //#100000 $finish;
 
endmodule
 
3 while
 
module whilexh;
reg clock;
initial
begin
clock =