xilinx_ug472_7Series_Clocking 阅读记录

Overview

7 Series FPGA High-Level Clock Architecture View

Clock Region in Virtex-7 FPGAs (Right Side)

Basic View of Clock Region

BUFG/BUFH/CMT Clock Region Detail

BUFR/BUFMR/BUFIO Clock Region Detail

BUFMR Primitive

Clock Connectivity

重点看各个时钟模块的输入输出

Use Cases

其他

Freq

• M–>CLKFBOUT_MULT_F
• D–>DIVCLK_DIVIDE
• O–>CLKOUT_DIVIDE

Limitations

In general, the major limitations are VCO operation range, input frequency, duty cycle programmability, and phase shift. In addition, there are connectivity limitations to other clocking elements (pins, GTs, and clock buffers).

下面贴出DS182中的MMCM相关参数

相移

Static Phase Shift Mode

The static phase shift (SPS) resolution in time units is defined as

Since the VCO can provide eight phase shifted clocks at 45° each; always providing possible settings for 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315° of phase shift. The higher the VCO frequency is, the smaller the phase-shift resolution.

Interpolated Fine Phase Shift in Fixed or Dynamic Mode in the MMCM

IFPS模式的相移和CLKOUT_DIVIDE的值无关，仅仅取决于VCO的频率，输出时钟的相移以1/56/Freq_vco的步进量线性递增，以360°循环。

Interpolated fine phase shift (IFPS) mode in the MMCM has linear shift behavior independent of the CLKOUT_DIVIDE value and the phase shift resolution only depends on the VCO frequency. In this mode the output clocks can be rotated 360° round robin in linear increments of 1/56th of the VCO period.

If the VCO runs at 600 MHz, then the phase resolution is approximately (rounded) 30 ps and at 1.6 GHz is approximately (rounded) 11 ps

There is no maximum phase shift or phase-shift overflow. An entire clock period (360 degrees) can always be phase shifted regardless of frequency.When the end of the period is reached, the phase shift wraps around round-robin style.

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结合器件视图进行理解

下面的叙述是基于XCV7485T-2FFG1927芯片在14.4版本的PlanAhead。

打开Device视图，能看到类似下图的视图，其中，XMYN表征的是时钟区域，另外还能看到有几个地方貌似是黑色空白的地方（已用方框框出），这些地方其实不是空无一物，而是放置了PCIE、XADC、DNA PORT、BSCAN、ICAP、FRAME_ECC、STARTUP等BEL的地方。

打开Clock Recources视图，可以看到FPGA器件的所有时钟资源，可以将某个时钟资源进行MARK，这样就可以观测到它的位置信息等属性，

• The global clock buffer can drive into every region through the HROW even if not physically located there。
• The horizontal clock buffers (BUFH) drive through the HROW to every clocking point in the region。
• The BUFIO only drives I/O clocking resources while the BUFR drives I/O resources and logic resources。

下图所示的是BUFG资源，它位于FPGA的中心位置，将其放大，可以观测到它的输入输出，还可以通过属性窗口观测到它的其他信息，

单就某个时钟区域具体而言，其图如下，图的中心处的一条横线就是HROW，在图中标出了A、B、C、D、E等区域，并MARK了一个区域，各个区域的含义如下，

区域	描述
A区域	IO Bank
B区域	IN FIFO及OUT FIFO
C区域	MMCM及PLL等
D区域	DSP48
E区域	Block RAM
MARK区域	BUFR、BUFIO等

在两个时钟区域的交界处，会有BUFH资源，如下图所示，