AHB总线信号的产生

`timescale 1ns/1ns 
module bus_wr_tb;
reg clk;
reg cs;//
reg wr;//写入地址
reg [31:0] addr;//32bit地址总线
reg [31:0] data;//32bit数据总线
initial
begin
cs=1'b1; wr=1'b1;//初始化
    #30;
    bus_wr(32'h1100008a, 32'h11113000);//调用任务
    bus_wr(32'h1100009a, 32'h11113001);
    bus_wr(32'h110000aa, 32'h11113002);
    bus_wr(32'h110000ba, 32'h11113003);
    bus_wr(32'h110000ca, 32'h11113004);
    addr=32'bx; data=32'bx;
  end
initial clk=1;//周期为10
  always #5 clk=~clk;
  task bus_wr;
  input [31:0] ADDR;
  input [31:0] DATA;
  begin
    cs=1'b0; wr=1'b0;
    addr=ADDR;
    data=DATA;
    #30 cs=1'b1; wr=1'b1;
  end
 endtask
endmodule

 

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