HDLBits刷题之Circuits-＞Combinational Logic-＞Karnaugh Map to Circuit

目录

Kmap1

 Write your solution here

Kmap2

 Write your solution here

Kmap3

 Write your solution here

Kmap4

 Write your solution here

Exams/ece241 2013 q2

Write your solution here

Exams/m2014 q3

Write your solution here

 Exams/2012 q1g

Write your solution here 

Exams/ece241 2014 q3

Write your solution here

---

Kmap1

Implement the circuit described by the Karnaugh map below.

Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if your reduction is equivalent, and we can check whether you can translate a k-map into a circuit.

 Write your solution here

module top_module(
    input a,
    input b,
    input c,
    output out  ); 

    assign out = a | b | c;
    
endmodule

Kmap2

Implement the circuit described by the Karnaugh map below.

Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if your reduction is equivalent, and we can check whether you can translate a k-map into a circuit.

 Write your solution here

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 

    //assign out = (~a)&(~c)&(~d) | (~a)&(~b)&(~c)&d | a&(~b)&(~c) | (~a)&b&c | a&c&d | (~a)&(~b)&c&(~d);
    assign out = ~a&~d | ~b&~c | ~a&b&c | a&c&d;
    
endmodule

Kmap3

Implement the circuit described by the Karnaugh map below.

Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if your reduction is equivalent, and we can check whether you can translate a k-map into a circuit.

 Write your solution here

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 

    assign out = a | (~b)&c;
//出现的d可以当作0，也可以当作1。
//“!”表示逻辑取反，“~”表示按位取反
//当面对位宽为1时:两个操作符的作用相同。
//当位宽不为1时:
//“~”会将变量的各个位依次取反如：a[3:0] ={1,0,1,1} ， ~a ={0,1,0,0};
//“!”会将变量作为一个值去做处理，非0为1：a[3:0] ={1,0,1,1} ，a=11，!a=0。a[3:0] ={0,0,0,0} ，a=0，!a=1
endmodule

Kmap4

Implement the circuit described by the Karnaugh map below.

Try to simplify the k-map before coding it. Try both product-of-sums and sum-of-products forms. We can't check whether you have the optimal simplification of the k-map. But we can check if your reduction is equivalent, and we can check whether you can translate a k-map into a circuit.

 Write your solution here

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 

    assign out = (~a)&(b)&(~c)&(~d) | (a)&(~b)&(~c)&(~d)
        | (~a)&(~b)&(~c)&(d) | (a)&(b)&(~c)&(d)
        | (~a)&(b)&(c)&(d) | (a)&(~b)&(c)&(d)
        | (~a)&(~b)&(c)&(~d) | (a)&(b)&(c)&(~d);
// +==|,*==&
//=（a’bc’d’+ab’c’d’）+（a’b’c’d+abc’d）+（a’bcd+ab’cd）+（a’b’cd’+abcd’）
//=(a^b)c’d’ + (a^b’)c’d + (a^b)cd + (a^b’)cd’
//=(a^b)&(c^d’) + (a^b’)&(c^d)  
//=(a^b)&(c^d)’ + (a^b)’&(c^d)  
//=(a^b)^(c^d)
    
    //公式：(ab)’=a’+b’,(a+b)’=a’b’,(a^b)=ab’+a’b,a’a=0
    //(a^b)’= (ab’+a’b)’ =  (ab’)’(a’b)’ =(a’+b)(a+b’) = a’a+a’b’+ab+b’b =a’b’+ab=a^b’
    
endmodule

Exams/ece241 2013 q2

A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively.

Determine the output out_sop in minimum SOP form, and the output out_pos in minimum POS form.

Write your solution here

module top_module (
    input a,
    input b,
    input c,
    input d,
    output out_sop,
    output out_pos
); 

    //SOP form 即与或式，对应于卡诺图就是圈1即可(画大圈可把d圈进来尽可能大，多余的d不圈)
	//POS form 即或与式, 对应于卡诺图就是圈0后，整体取反（d同理）
    // ab\cd  00  01  11  10
    //   00   0   0   d   1
    //   01   d   0   1   0
    //   11   d   0   1   0
    //   10   0   0   0   0
    assign out_sop = c&d | (~a)&(~b)&c;
    assign out_pos = ~((~c) | b&(~d) | a&(~b));
    
endmodule

Exams/m2014 q3

Consider the function f shown in the Karnaugh map below.

Implement this function. d is don't-care, which means you may choose to output whatever value is convenient.

Write your solution here

module top_module (
    input [4:1] x, 
    output f );

    assign f = (~x[1])&x[3] | x[2]&(~x[3])&x[4];
endmodule

 Exams/2012 q1g

Consider the function f shown in the Karnaugh map below. Implement this function.

(The original exam question asked for simplified SOP and POS forms of the function.)

Write your solution here 

module top_module (
    input [4:1] x,
    output f
); 
	//四个角构成一个圈
    assign f = (~x[1])&x[3] | (~x[2])&(~x[4]) | x[2]&x[3]&x[4];
    
endmodule

Exams/ece241 2014 q3

For the following Karnaugh map, give the circuit implementation using one 4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using as few as possible. You are not allowed to use any other logic gate and you must use a and b as the multiplexer selector inputs, as shown on the 4-to-1 multiplexer below.

You are implementing just the portion labelled top_module, such that the entire circuit (including the 4-to-1 mux) implements the K-map.

(The requirement to use only 2-to-1 multiplexers exists because the original exam question also wanted to test logic function simplification using K-maps and how to synthesize logic functions using only multiplexers. If you wish to treat this as purely a Verilog exercise, you may ignore this constraint and write the module any way you wish.)

Write your solution here

module top_module (
    input c,
    input d,
    output [3:0] mux_in
); 
    assign mux_in[0] = c?1:(d?1:0);
    assign mux_in[1] = 0;
    assign mux_in[3] = c?(d?1:0):0;//注意图是10，而不是11
    assign mux_in[2] = d?0:1;
endmodule