（14） ZYNQ AXI4-Lite总线简介（学无止境）

1 应用领域

ZYNQ FPGA PS与PL交互主要是通过AXI4-Lite总线。通过寄存器的方式进行数据交互，每个寄存器有对应的地址。地址深度可以根据用户随意设置，最高可以支持64K。

2 信号说明

AXI4-Lite总线信号如下：
// Global Clock Signal
input wire  S_AXI_ACLK,//时钟
// Global Reset Signal. This Signal is Active LOW
input wire  S_AXI_ARESETN,//复位信号
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,//写地址
// Write channel Protection type. This signal indicates the
    // privilege and security level of the transaction, and whether
    // the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,//数据安全级别和权限
// Write address valid. This signal indicates that the master signaling
    // valid write address and control information.
input wire  S_AXI_AWVALID,//写地址有效
// Write address ready. This signal indicates that the slave is ready