二进制码和格雷码之间的转换
一、二进制码与格雷码转换原理
(1)二进制码转换格雷码
二进制码 Bi Bi-1 Bi-2 ... B1 B0
^ ^ ^ ^ ^
B >>1 0 Bi Bi-1 ... B2 B1
格雷码 Gi Gi-1 Gi-2 ... G1 G0
(2)格雷码转换二进制码
Bi = Gi ;
Bi-1 = Bi ^ Gi-1 = Gi ^ Gi-1 ;
Bi-2 = Bi-1 ^ Gi-2 = Gi ^ Gi-1 ^ Gi-2 ;
:
:
:
B3 = B4 ^ G3 = Gi ^ Gi-1 ^ Gi-2 ... ^ G3;
B2 = B3 ^ G2 = Gi ^ Gi-1 ^ Gi-2 ... ^ G3 ^ G2;
B1 = B2 ^ G1 = Gi ^ Gi-1 ^ Gi-2 ... ^ G3 ^ G2 ^ G1;
B0 = B2 ^ G1 = Gi ^ Gi-1 ^ Gi-2 ... ^ G3 ^ G2 ^ G1 ^ G0;
(3)二进制码与格雷码转换的Verilog实现
数值回环,输入二进制码数值,内部转换格雷码,再次转换为二进制码,验证代码的功能
module class_7_GB_BG#(
parameter WIDTH = 4
)(
input [WIDTH-1:00] i_bin_data ,
output [WIDTH-1:00] o_grey_data ,
output reg [WIDTH-1:00] o_bin_data
);
/********二进制码转换格雷码***********************/
assign o_grey_data = (i_bin_data >> 1) ^ i_bin_data;
/********二进制码转换格雷码***********************/
/********格雷码转换二进制码***********************/
integer i;
always@(o_grey_data)
begin
for(i=0;i<WIDTH;i=i+1)
begin
o_bin_data[i] <= ^ (o_grey_data >> i);
end
end
/********格雷码转换二进制码***********************/
endmodule
(4)仿真testbench文件
module tb_class7#(
parameter WIDTH = 4
);
reg [WIDTH-1:00] i_bin_data;
wire [WIDTH-1:00] o_grey_data;
wire [WIDTH-1:00] o_bin_data;
class_7_GB_BG#(
.WIDTH(WIDTH)
)u_class_7_GB_BG(
.i_bin_data (i_bin_data) ,
.o_grey_data (o_grey_data),
.o_bin_data (o_bin_data)
);
initial begin
i_bin_data = 0;
#100;
i_bin_data = 1;
#100;
i_bin_data = 2;
#100;
i_bin_data = 3;
#100;
i_bin_data = 4;
#100;
i_bin_data = 5;
#100;
i_bin_data = 6;
#100;
i_bin_data = 7;
#100;
i_bin_data = 8;
#100;
i_bin_data = 9;
#100;
i_bin_data = 10;
#100;
i_bin_data = 11;
#100;
i_bin_data = 12;
#100;
i_bin_data = 13;
#100;
i_bin_data = 14;
#100;
i_bin_data = 15;
#100;
end
endmodule
(5)仿真结果
仿真输出预计值对照表
仿真测试值