【手撕代码-序列检测1011001-每次输入2bit】

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最新推荐文章于 2023-04-28 00:14:47 发布

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分类专栏： verilog学习

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Verilog 序列检测状态图数字逻辑硬件描述语言

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题目要求：

请实现对（1011001）2的序列检测功能，模块每拍并行输入2bit，且顺序为高位先输入，当检测到序列，输出一拍高电平脉冲。序列检测题的关键是画出状态图

代码实现：

/*
 * @Author: yaohao 
 * @Date: 2022-06-23 19:22:44 
 * @Last Modified by: yaohao
 * @Last Modified time: 2022-06-23 19:43:43
 */

module check_2bit (
    input clk,
    input rst,
    input [1:0]data_in,
    output reg data_out//flag
);
    reg [1:0] state, n_state;
    parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;

    always @(posedge clk or negedge rst) begin  //状态记忆
        if(!rst) 
            state <= S0;
        else 
            state <= n_state;
    end

    always @(*) begin   //状态转移
        n_state = S0;
        case(state)
            S0: begin
                if(data_in == 2'b10)
                    n_state = S1;
                else 
                    n_state = S0;
                end
            S1:   begin
                if(data_in == 2'b11)
                    n_state = S2;
                else if(data_in == 2'b10)
                    n_state = S1;
                else 
                    n_state = S0;
                end
            S2: begin
                if(data_in == 2'b00)
                    n_state = S3;
                else if(data_in == 2'b10)
                    n_state = S1;
                else 
                    n_state = S0;
                end
            S3: begin 
                if(data_in == 2'b10)
                    n_state = S1;
                else 
                    n_state = S0;
                end
        endcase
            end
    always @(posedge clk or negedge rst) begin
        if(!rst)
            data_out <= 0;
        else begin
            data_out <= 0;
        case(state)
            S0: data_out <= 0;
            S1: data_out <= 0;
            S2: data_out <= 0;
            S3: data_out <= 1;
        endcase
        end
        end

endmodule //check_2bit