module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
wire enass,enamm,enahh;
assign enass = ena;
assign enamm = ena&&(ss==8'h59);
assign enahh = enamm&&(mm==8'h59);
bcd U1(clk,reset,enass,ss);
bcd U2(clk,reset,enamm,mm);
bcdhh U3(clk,reset,enahh,hh);
always@(posedge clk) begin
if(reset)
pm<=1'b0;
else if(enahh&&(hh==8'h11))
pm<=~pm;
else
pm<=pm;
end
endmodule
module bcd(input clk,input reset, input ena, output [7:0] q);
always@(posedge clk) begin
if(reset)
q<=0;
else if(ena) begin
if(q==8'h59)
q<=0;
else begin
if(q[3:0]==9) begin
q[3:0]<=0;
q[7:3]<=q[7:3]+1'b1;
end
else
q[3:0]<=q[3:0]+1'b1;
end
end
end
endmodule
module bcdhh(input clk,input reset, input ena, output [7:0] q);
always@(posedge clk) begin
if(reset)
q<=8'h12;
else begin
if(ena) begin
if(q==8'h12)
q<=8'h01;
else begin
if(q[3:0]==4'd9) begin
q[3:0]<=0;
q[7:3]<=q[7:3]+1;
end
else
q[3:0]<=q[3:0]+1;
end
end
end
end
endmodule
Count clock
最新推荐文章于 2023-03-12 19:12:28 发布