More Circuits

Rule90

法一： 

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    
    always@(posedge clk)begin
        if(load)begin
            q<=data;
        end
        else begin
            //q<={1'b0^q[510],q[511:2]^q[509:0] ,q[1]^1'b0};//两头分别自己算，中间同下；
            q<={1'b0,q[511:1]} ^ {q[510:0],1'b0}; //整体的左边^整体的右边；
        end
    end

endmodule

法二：

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    
    always@(posedge clk)begin
        if(load)begin
            q<=data;
        end
        else begin
            q[0]<=q[1]^1'b0;
    		q[511]<=1'b0^q[510];
        	for(int i=1;i<511;i=i+1)begin
                q[i]<=q[i+1]^q[i-1];
    		end
        end
    end

endmodule

Rule110

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q
); 
    always@(posedge clk)begin
        if(load)begin
            q<=data;
        end
        else begin
            q[0]<=~q[1]&1'b0 | q[0]^1'b0;
            q[511]<=~1'b0&q[510] | q[511]^q[510];
        	for(int i=1;i<511;i=i+1)begin
                q[i]<=~q[i+1]&q[i-1] | q[i]^q[i-1]; 
                //令q[i+1]=a,q[i]=b,q[i-1]=c,根据真值表化简得到q[i]=~a&c | b^c;
    		end
        end
    end
endmodule