·Four-input gates
Build a combinational circuit with four inputs, in[3:0].
There are 3 outputs:
- out_and: output of a 4-input AND gate.
- out_or: output of a 4-input OR gate.
- out_xor: output of a 4-input XOR gate.
module top_module(
input [3:0] in,
output out_and,
output out_or,
output out_xor);
and U1(out_and,in[3],in[2],in[1],in[0]);
or U2(out_or,in[3],in[2],in[1],in[0]);
xor U3(out_xor,in[3],in[2],in[1],in[0]);
endmodule
·Vector reversal
Given an 8-bit input vector [7:0], reverse its bit ordering.
module top_module(
input [7:0] in,
output [7:0] out);
assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};
endmodule
几个误区:
1、assign out[7:0] = in[0:7]是不被允许的,part-select要与declaration方向一致
2、循环语句不符合硬件电路思维,且不可综合,assign语句使用过多
// I know you're dying to know how to use a loop to do this:
// Create a combinational always block. This creates combinational logic that computes the same result
// as sequential code. for-loops describe circuit *behaviour*, not *structure*, so they can only be used
// inside procedural blocks (e.g., always block).
// The circuit created (wires and gates) does NOT do any iteration: It only produces the same result
// AS IF the iteration occurred. In reality, a logic synthesizer will do the iteration at compile time to
// figure out what circuit to produce. (In contrast, a Verilog simulator will execute the loop sequentially
// during simulation.)
always @(*) begin
for (int i=0; i<8; i++) // int is a SystemVerilog type. Use integer for pure Verilog.
out[i] = in[8-i-1];
end