· DFFs and gates
注意组合逻辑Z的位置,暂时可按如下方式考虑(由于Z无寄存器构成流水线,需单独从always的时序模块中拎出来,用数据流形式描述)
module top_module (
input clk,
input x,
output z
);
reg q2,q1,q0;
assign z = ~(q2 | q1 | q0);
always @(posedge clk) begin
q2 <= x ^ q2;
q1 <= x & ~q1;
q0 <= x | ~q0;
end
endmodule
·Edge capture register
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
reg [31:0] o;
always @(posedge clk) begin
o <= in;
if (reset)
out <= 32'h0;
else
out <= o & ~in | out;
end
endmodule
细细品味这个 out <= o & ~in | out; 真的很绝!
·Dualedge
module top_module(
input clk,
input d,
output q);
reg p, n;
// A positive-edge triggered flip-flop
always @(posedge clk)
p <= d ^ n;
// A negative-edge triggered flip-flop
always @(negedge clk)
n <= d ^ p;
// Why does this work?
// After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d.
// After negedge clk, n changes to d^p. Thus q = (p^n) = (p^d^p) = d.
// At each (positive or negative) clock edge, p and n FFs alternately
// load a value that will cancel out the other and cause the new value of d to remain.
assign q = p ^ n;
// Can't synthesize this.
/*always @(posedge clk, negedge clk) begin
q <= d;
end*/
endmodule
掌握这个 a^b^b=a, 也很绝!