systemverilog中立即断言和并发断言

1. 简单的立即断言
   测试平台的过程代码可以检查待测信号的设计值和测试平台的信号值，并且在存在问题的时候采取相应的行动。
   断言里面的逻辑条件跟if语句里面的比较条件是相反的。设计者应该期望括号内的表达式为真，否则输出一个错误。

bus.cb.request <= 1;
repeat(2) @bus.cb;
a1: assert (bus.cb.grant== 2'b01);

失败的立即断言立即给出错误消息：

"test.sv",7:top.t1.a1:started at 55ns failed at 55ns
offending'(bus.cb.grant == 2'b01)'

2.定制的立即断言

a1: assert (bus.cb.grant== 2'b01)
else $error("Grant not asseted");

错误消息：

"test.sv",7:top.t1.a1:started at 55ns failed at 55ns
offending'(bus.cb.grant == 2'b01)'
Error: "test.sv",7:top.t1.a1: 55ns时
Granted not asserted

3.并发断言
另外一种就是并发断言，你可以任务它是一个连续运行的模块，它为整个仿真过程检查信号的值。需要在断言内指定一个采样时钟。
检查X/Z的并发断言

interface arb_if(input bit clk);
  logic [1:0] grant, request;
  logic rst;
  
  property request_2state；
    @(posedge clk) disable iff (rst);
    $isunknown(request) == 0; //确保没有x或z
  endproperty
  assert_request_2state: assert property (requeset_2state);
endinterface

4.assert在sequence中的使用

class case0_sequence extends uvm_sequence #(my_transaction);
   function  new(string name= "case0_sequence");
      super.new(name);
   endfunction 
   virtual task pre_body();
      if(starting_phase != null) 
         starting_phase.raise_objection(this);
   endtask
   virtual task post_body();
      if(starting_phase != null) 
         starting_phase.drop_objection(this);
   endtask
   virtual task body();
      my_transaction m_tr;
      ip_transaction ip_tr;
      byte unsigned     data_q[];
      int  data_size;
      repeat (10) begin
         ip_tr = new("ip_tr");
         assert(ip_tr.randomize() with {ip_tr.src_ip == 'h9999; ip_tr.dest_ip == 'h10000;}) //
         //ip_tr.print();
         data_size = ip_tr.pack_bytes(data_q) / 8; 
         m_tr = new("m_tr");
         assert(m_tr.randomize with{m_tr.pload.size() == data_size;}); //
         for(int i = 0; i < data_size; i++) begin
            m_tr.pload[i] = data_q[i];
         end
         `uvm_send(m_tr)
      end
      #100;
   endtask
   `uvm_object_utils(case0_sequence)
endclass