Qsys生成simulator时产生的tcl脚本建立仿真

用Qsys生成simulator时产生的tcl脚本建立仿真的过程：

对QSYS的仿真采用其自己生成的sim文件夹中的tcl脚本，不用自己在do文件中加入IP文件列表了，可以比较快速的建立qsys的仿真工程。针对该qsys的testbench还是得自己建的。

过程如下：

1. 针对qsys核建立测试工程
2. 将msim_setup.tcl中的# # TOP-LEVEL TEMPLATE - BEGIN 到# # TOP-LEVEL TEMPLATE - END 复制到另外一个文件，保存为mentor.do
3. 修改 mentor.do文件 中路径和需要的编译选项。(见后面附录)
4. 在mentor.do目录下，cmd命令执行vsim -do mentor.do
   至此结束。

在mentor.do文件中包含了对库文件的编译，每一次都编译再仿真的话启动速度会很慢。因此在第一次编译后，可以对mentor.do文件进行修改，优化掉这一段。或者只在modelsim中执行下面一段。

vlog ../*.v

set TOP_LEVEL_NAME DMA_sys_TOP_tb

set USER_DEFINED_ELAB_OPTIONS -voptargs="+acc"

elab

# # Run the simulation.

log -r /*

do wave.do

run 5us

附修改后的mentor.do文件，红色是修改的地方

# ----------------------------------------

# # TOP-LEVEL TEMPLATE - BEGIN

# #

# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to

# # construct paths to the files required to simulate the IP in your Quartus

# # project. By default, the IP script assumes that you are launching the

# # simulator from the IP script location. If launching from another

# # location, set QSYS_SIMDIR to the output directory you specified when you

# # generated the IP script, relative to the directory from which you launch

# # the simulator.

# #

# set QSYS_SIMDIR <script generation output directory>

set QSYS_SIMDIR D:/Work/FPGA/DMA/selfdma_v3_addr_Sim_0425/dd4_sys/sim

# #

# # Source the generated IP simulation script.

source $QSYS_SIMDIR/mentor/msim_setup.tcl

# #

# # Set any compilation options you require (this is unusual).

# set USER_DEFINED_COMPILE_OPTIONS <compilation options>

# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>

# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>

# #

# # Call command to compile the Quartus EDA simulation library.

dev_com

# #

# # Call command to compile the Quartus-generated IP simulation files.

com

# #

# # Add commands to compile all design files and testbench files, including

# # the top level. (These are all the files required for simulation other

# # than the files compiled by the Quartus-generated IP simulation script)

# #

# vlog <compilation options> <design and testbench files>

vlog ../*.v

 

# #

# # Set the top-level simulation or testbench module/entity name, which is

# # used by the elab command to elaborate the top level.

# #

# set TOP_LEVEL_NAME <simulation top>

set TOP_LEVEL_NAME DMA_sys_TOP_tb

# #

# # Set any elaboration options you require.

# set USER_DEFINED_ELAB_OPTIONS <elaboration options>

set USER_DEFINED_ELAB_OPTIONS -voptargs="+acc"

# #

# # Call command to elaborate your design and testbench.

elab

# #

# # Run the simulation.

# run -a

log -r /*

do wave.do

run 5us

# #

# # Report success to the shell.

# exit -code 0

# #

# # TOP-LEVEL TEMPLATE - END

# ----------------------------------------